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    Searched refs:NewDestReg (Results 1 - 6 of 6) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86FixupBWInsts.cpp 287 Register NewDestReg;
293 if (!getSuperRegDestIfDead(MI, NewDestReg))
298 BuildMI(*MF, MI->getDebugLoc(), TII->get(New32BitOpcode), NewDestReg);
314 Register NewDestReg;
315 if (!getSuperRegDestIfDead(MI, NewDestReg))
324 TRI->getSubRegIndex(NewDestReg, OldDest.getReg()))
333 BuildMI(*MF, MI->getDebugLoc(), TII->get(X86::MOV32rr), NewDestReg)
339 if (Op.getReg() != (Op.isDef() ? NewDestReg : NewSrcReg))
347 Register NewDestReg;
348 if (!getSuperRegDestIfDead(MI, NewDestReg))
    [all...]
X86RegisterInfo.cpp 703 Register NewDestReg = MI.getOperand(0).getReg();
706 TII->copyPhysReg(*MI.getParent(), II, MI.getDebugLoc(), NewDestReg, BasePtr,
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64CondBrTuning.cpp 101 Register NewDestReg = MI.getOperand(0).getReg();
103 NewDestReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
106 TII->get(NewOpc), NewDestReg);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMFastISel.cpp 592 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
595 DbgLoc, TII.get(Opc), NewDestReg)
599 return NewDestReg;
608 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
611 TII.get(ARM::t2LDRi12), NewDestReg)
616 TII.get(ARM::LDRi12), NewDestReg)
619 DestReg = NewDestReg;
2988 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
2990 TII.get(ARM::t2LDRi12), NewDestReg)
2993 DestReg = NewDestReg;
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUMachineCFGStructurizer.cpp 66 void replaceDef(unsigned OldDestReg, unsigned NewDestReg);
206 void PHILinearize::replaceDef(unsigned OldDestReg, unsigned NewDestReg) {
207 phiInfoElementSetDef(findPHIInfoElement(OldDestReg), NewDestReg);
2430 Register NewDestReg = MRI->createVirtualRegister(RegClass);
2431 LRegion->replaceRegisterInsideRegion(PHIDest, NewDestReg, false, MRI);
2434 TII->get(TargetOpcode::PHI), NewDestReg);
2435 LLVM_DEBUG(dbgs() << "Split Entry PHI " << printReg(NewDestReg, TRI)
SIInstrInfo.cpp 811 MCRegister NewDestReg = RI.get32BitRegister(DestReg);
820 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), NewDestReg)
831 copyPhysReg(MBB, MI, DL, NewDestReg, NewSrcReg, KillSrc);
841 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), NewDestReg)
846 auto MIB = BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_sdwa), NewDestReg)
855 .addReg(NewDestReg, RegState::Implicit | RegState::Undef);

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