| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| R600ExpandSpecialInstrs.cpp | 31 void SetFlagInNewMI(MachineInstr *NewMI, const MachineInstr *OldMI,
61 void R600ExpandSpecialInstrsPass::SetFlagInNewMI(MachineInstr *NewMI,
66 TII->setImmOperand(*NewMI, Op, Val);
251 MachineInstr *NewMI =
255 NewMI->bundleWithPred();
257 TII->addFlag(*NewMI, 0, MO_FLAG_MASK);
260 TII->addFlag(*NewMI, 0, MO_FLAG_NOT_LAST);
262 SetFlagInNewMI(NewMI, &MI, R600::OpName::clamp);
263 SetFlagInNewMI(NewMI, &MI, R600::OpName::literal);
264 SetFlagInNewMI(NewMI, &MI, R600::OpName::src0_abs)
[all...] |
| GCNDPPCombine.cpp | 567 auto *NewMI = BB->getParent()->CloneMachineInstr(&OrigMI);
568 BB->insert(OrigMI, NewMI);
569 if (TII->commuteInstruction(*NewMI)) {
570 LLVM_DEBUG(dbgs() << " commuted: " << *NewMI);
572 createDPPInst(*NewMI, MovMI, CombOldVGPR, OldOpndValue, CombBCZ,
579 NewMI->eraseFromParent();
|
| R600OptimizeVectorRegisters.cpp | 215 MachineInstr *NewMI =
217 LLVM_DEBUG(dbgs() << " ->"; NewMI->dump(););
229 RSI->Instr = NewMI;
233 return NewMI;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/CSKY/MCTargetDesc/ |
| CSKYInstPrinter.cpp | 64 const MCInst *NewMI = MI;
66 if (NoAliases || !printAliasInstr(NewMI, Address, STI, O))
67 printInstruction(NewMI, Address, STI, O);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86FixupLEAs.cpp | 143 MachineInstr *NewMI =
153 return NewMI;
399 MachineInstr *NewMI = nullptr;
411 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
416 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
432 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
435 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
442 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
446 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
453 MBB.getParent()->substituteDebugValuesForInst(*I, *NewMI, 1)
[all...] |
| X86TileConfig.cpp | 134 MachineInstr *NewMI = nullptr;
165 NewMI = addFrameReference(
170 ConstMI = NewMI;
171 LIS.InsertMachineInstrInMaps(*NewMI);
181 NewMI = addFrameReference(
186 SlotIndex SIdx = LIS.InsertMachineInstrInMaps(*NewMI);
|
| X86LowerTileCopy.cpp | 113 MachineInstr *NewMI =
116 MachineOperand &MO = NewMI->getOperand(2);
121 NewMI = addFrameReference(BuildMI(MBB, MI, DL, TII->get(Opc), DstReg),
|
| X86FixupBWInsts.cpp | 445 if (MachineInstr *NewMI = tryReplaceInstr(MI, MBB))
446 MIReplacements.push_back(std::make_pair(MI, NewMI));
454 MachineInstr *NewMI = MIReplacements.back().second;
456 MBB.insert(MI, NewMI);
|
| X86InstrInfo.cpp | 1153 MachineInstr &NewMI = *std::prev(I);
1154 NewMI.substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
1347 MachineInstr *NewMI = MIB;
1355 LV->getVarInfo(InRegLEA).Kills.push_back(NewMI);
1400 MachineInstr *NewMI = nullptr;
1417 NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
1451 NewMI = MIB;
1484 NewMI = addOffset(MIB, 1);
1506 NewMI = addOffset(MIB, -1);
1549 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonHazardRecognizer.cpp | 56 MachineInstr *NewMI =
59 if (Resources->canReserveResources(*NewMI))
63 MF->DeleteMachineInstr(NewMI);
127 MachineInstr *NewMI =
130 assert(Resources->canReserveResources(*NewMI));
131 Resources->reserveResources(*NewMI);
132 MF->DeleteMachineInstr(NewMI);
|
| HexagonNewValueJump.cpp | 682 MachineInstr *NewMI;
693 NewMI = BuildMI(*MBB, jmpPos, dl, QII->get(opc))
699 NewMI = BuildMI(*MBB, jmpPos, dl, QII->get(opc))
704 assert(NewMI && "New Value Jump Instruction Not created!");
705 (void)NewMI;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/MCTargetDesc/ |
| RISCVInstPrinter.cpp | 70 const MCInst *NewMI = MI;
75 NewMI = const_cast<MCInst *>(&UncompressedMI);
76 if (NoAliases || !printAliasInstr(NewMI, Address, STI, O))
77 printInstruction(NewMI, Address, STI, O);
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| TargetInstrInfo.cpp | 168 bool NewMI, unsigned Idx1,
219 if (NewMI) {
250 MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr &MI, bool NewMI,
262 return commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
518 MachineInstr *NewMI =
520 MachineInstrBuilder MIB(MF, NewMI);
553 NewMI->tieOperands(TiedTo, NewMI->getNumOperands() - 1);
557 return NewMI;
598 MachineInstr *NewMI = nullptr
[all...] |
| ModuloSchedule.cpp | 136 MachineInstr *NewMI = cloneInstr(CI, MaxStageCount, StageNum);
137 updateInstruction(NewMI, false, MaxStageCount, StageNum, VRMap);
138 KernelBB->push_back(NewMI);
139 InstrMap[NewMI] = CI;
147 MachineInstr *NewMI = MF.CloneMachineInstr(&*I);
148 updateInstruction(NewMI, false, MaxStageCount, 0, VRMap);
149 KernelBB->push_back(NewMI);
150 InstrMap[NewMI] = &*I;
219 MachineInstr *NewMI =
221 updateInstruction(NewMI, false, i, (unsigned)StageNum, VRMap)
[all...] |
| FixupStatepointCallerSaved.cpp | 474 MachineInstr *NewMI =
476 MachineInstrBuilder MIB(MF, NewMI);
492 NewIndices.push_back(NewMI->getNumOperands());
502 NewIndices.push_back(NewMI->getNumOperands());
538 NewMI->setMemRefs(MF, MI.memoperands());
549 NewMI->addMemOperand(MF, MMO);
553 MI.getParent()->insert(MI, NewMI);
555 LLVM_DEBUG(dbgs() << "rewritten statepoint to : " << *NewMI << "\n");
557 return NewMI;
|
| MachineLoopUtils.cpp | 48 MachineInstr *NewMI = MF.CloneMachineInstr(&MI);
49 NewBB->insert(InsertPt, NewMI);
50 for (MachineOperand &MO : NewMI->defs()) {
|
| TwoAddressInstructionPass.cpp | 544 MachineInstr *NewMI = TII->commuteInstruction(*MI, false, RegBIdx, RegCIdx);
546 if (NewMI == nullptr) {
551 LLVM_DEBUG(dbgs() << "2addr: COMMUTED TO: " << *NewMI);
552 assert(NewMI == MI &&
590 MachineInstr *NewMI = TII->convertToThreeAddress(MFI, *mi, LV);
593 if (!NewMI)
597 LLVM_DEBUG(dbgs() << "2addr: TO 3-ADDR: " << *NewMI);
600 LIS->ReplaceMachineInstrInMaps(*mi, *NewMI);
606 assert(NewMI->getNumExplicitDefs() == 1);
610 auto NewIt = NewMI->defs().begin()
[all...] |
| RegisterCoalescer.cpp | 883 MachineInstr *NewMI =
885 if (!NewMI)
891 if (NewMI != DefMI) {
892 LIS->ReplaceMachineInstrInMaps(*DefMI, *NewMI);
894 MBB->insert(Pos, NewMI);
1337 MachineInstr &NewMI = *std::prev(MII);
1338 NewMI.setDebugLoc(DL);
1347 MachineOperand &DefMO = NewMI.getOperand(0);
1380 LIS->ReplaceMachineInstrInMaps(*CopyMI, NewMI);
1384 // NewMI may have dead implicit defs (E.g. EFLAGS for MOV<bits>r0 on X86)
[all...] |
| MachineCSE.cpp | 542 if (MachineInstr *NewMI = TII->commuteInstruction(*MI)) {
544 FoundCSE = VNT.count(NewMI);
545 if (NewMI != MI) {
547 NewMI->eraseFromParent();
856 MachineInstr &NewMI =
863 NewMI.setDebugLoc(EmptyDL);
865 NewMI.getOperand(0).setReg(NewReg);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyInstrInfo.h | 52 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
|
| WebAssemblyInstrInfo.cpp | 91 MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const {
100 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| Thumb2InstrInfo.h | 67 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
|
| A15SDOptimizer.cpp | 374 MachineInstr *NewMI = MRI->getVRegDef(Reg);
375 if (!NewMI)
377 Front.push_back(NewMI);
382 MachineInstr *NewMI = MRI->getVRegDef(MI->getOperand(1).getReg());
383 if (!NewMI)
385 Front.push_back(NewMI);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| LanaiInstrInfo.cpp | 513 MachineInstrBuilder NewMI =
520 NewMI.add(DefMI->getOperand(i));
524 NewMI.addImm(getOppositeCondition(LPCC::CondCode(CondCode)));
526 NewMI.addImm(CondCode);
527 NewMI.copyImplicitOps(MI);
533 NewMI.add(FalseReg);
534 NewMI->tieOperands(0, NewMI->getNumOperands() - 1);
537 SeenMIs.insert(NewMI);
545 NewMI->clearKillInfo()
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| SlotIndexes.h | 592 SlotIndex replaceMachineInstrInMaps(MachineInstr &MI, MachineInstr &NewMI) {
600 miEntry->setInstr(&NewMI);
602 mi2iMap.insert(std::make_pair(&NewMI, replaceBaseIndex));
|
