HomeSort by: relevance | last modified time | path
    Searched refs:NewOpcode (Results 1 - 25 of 40) sorted by relevancy

1 2

  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonCFGOptimizer.cpp 85 int NewOpcode = 0;
88 NewOpcode = Hexagon::J2_jumpf;
91 NewOpcode = Hexagon::J2_jumpt;
94 NewOpcode = Hexagon::J2_jumpfnewpt;
97 NewOpcode = Hexagon::J2_jumptnewpt;
103 MI.setDesc(TII->get(NewOpcode));
HexagonVLIWPacketizer.cpp 463 int NewOpcode;
465 NewOpcode = HII->getDotNewPredOp(MI, MBPI);
467 NewOpcode = HII->getDotNewOp(MI);
468 MI.setDesc(HII->get(NewOpcode));
473 int NewOpcode = HII->getDotOldOp(MI);
474 MI.setDesc(HII->get(NewOpcode));
892 int NewOpcode = HII->getDotNewOp(MI);
893 const MCInstrDesc &D = HII->get(NewOpcode);
HexagonInstrInfo.cpp 1557 unsigned NewOpcode = getInvertedPredicatedOpcode(opcode);
1558 Cond[0].setImm(NewOpcode);
3759 int NewOpcode = Hexagon::getPredNewOpcode(MI.getOpcode());
3760 if (NewOpcode >= 0)
3761 return NewOpcode;
4553 unsigned NewOpcode = getInvertedPredicatedOpcode(MI.getOpcode());
4562 NewOpcode = reversePrediction(NewOpcode);
4564 MI.setDesc(get(NewOpcode));
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
MVEVPTBlockPass.cpp 68 unsigned &NewOpcode) {
83 NewOpcode = VCMPOpcodeToVPT(CmpMI->getOpcode());
84 if (NewOpcode == 0)
264 unsigned NewOpcode;
266 if (MachineInstr *VCMP = findVCMPToFoldIntoVPST(MI, TRI, NewOpcode)) {
268 MIBuilder = BuildMI(Block, MI, DL, TII->get(NewOpcode));
  /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
XCoreRegisterInfo.cpp 137 int NewOpcode;
139 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
140 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
145 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
146 BuildMI(MBB, II, dl, TII.get(NewOpcode))
152 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
153 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/
ARCOptAddrMode.cpp 100 void changeToAddrMode(MachineInstr &Ldst, unsigned NewOpcode,
253 int NewOpcode = ARC::getPostIncOpcode(Ldst.getOpcode());
254 assert(NewOpcode > 0 && "No postincrement form found");
256 changeToAddrMode(Ldst, NewOpcode, NewBaseReg, Add.getOperand(2));
441 void ARCOptAddrMode::changeToAddrMode(MachineInstr &Ldst, unsigned NewOpcode,
459 Ldst.setDesc(AST->getInstrInfo()->get(NewOpcode));
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86FixupLEAs.cpp 405 unsigned NewOpcode = getADDrrFromLEA(MI.getOpcode());
411 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
416 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
428 unsigned NewOpcode = getINCDECFromLEA(MI.getOpcode(), IsINC);
432 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
435 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
439 unsigned NewOpcode = getADDriFromLEA(MI.getOpcode(), Disp);
442 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
446 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
X86InstrInfo.cpp 4164 unsigned NewOpcode = 0;
4167 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break;
4168 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break;
4169 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break;
4170 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break;
4171 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break;
4172 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break;
4173 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break;
4174 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break;
4175 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDILCFGStructurizer.cpp 197 void insertInstrEnd(MachineBasicBlock *MBB, int NewOpcode,
199 MachineInstr *insertInstrBefore(MachineBasicBlock *MBB, int NewOpcode,
201 MachineInstr *insertInstrBefore(MachineBasicBlock::iterator I, int NewOpcode);
202 void insertCondBranchBefore(MachineBasicBlock::iterator I, int NewOpcode,
205 MachineBasicBlock::iterator I, int NewOpcode,
432 int NewOpcode, const DebugLoc &DL) {
434 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DL);
441 int NewOpcode,
444 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DL);
454 MachineBasicBlock::iterator I, int NewOpcode) {
    [all...]
SIWholeQuadMode.cpp 744 unsigned NewOpcode = 0;
747 NewOpcode = AMDGPU::S_AND_B32_term;
750 NewOpcode = AMDGPU::S_AND_B64_term;
753 NewOpcode = AMDGPU::S_MOV_B32_term;
756 NewOpcode = AMDGPU::S_MOV_B64_term;
761 if (NewOpcode)
762 TermMI->setDesc(TII->get(NewOpcode));
SIISelLowering.h 74 unsigned NewOpcode) const;
76 unsigned NewOpcode) const;
SIShrinkInstructions.cpp 286 unsigned NewOpcode =
289 MI.setDesc(TII->get(NewOpcode));
  /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
LanaiRegisterInfo.cpp 228 unsigned NewOpcode = getOppositeALULoOpcode(MI.getOpcode());
233 BuildMI(*MI.getParent(), II, DL, TII->get(NewOpcode),
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/
MipsMCCodeEmitter.cpp 193 int NewOpcode = -1;
196 NewOpcode = Mips::MipsR62MicroMipsR6(Opcode, Mips::Arch_micromipsr6);
197 if (NewOpcode == -1)
198 NewOpcode = Mips::Std2MicroMipsR6(Opcode, Mips::Arch_micromipsr6);
201 NewOpcode = Mips::Std2MicroMips(Opcode, Mips::Arch_micromips);
204 if (NewOpcode == -1)
205 NewOpcode = Mips::Dsp2MicroMips(Opcode, Mips::Arch_mmdsp);
207 if (NewOpcode != -1) {
211 TmpInst.setOpcode (NewOpcode);
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZFrameLowering.cpp 601 unsigned NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset);
605 if (!NewOpcode) {
610 NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset);
611 assert(NewOpcode && "No restore instruction available");
614 MBBI->setDesc(ZII->get(NewOpcode));
SystemZInstrInfo.cpp 64 // each having the opcode given by NewOpcode.
66 unsigned NewOpcode) const {
107 unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm());
108 unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm());
125 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset);
126 assert(NewOpcode && "No support for huge argument lists yet");
127 MI->setDesc(get(NewOpcode));
957 unsigned NewOpcode;
959 NewOpcode = SystemZ::RISBG;
962 NewOpcode = SystemZ::RISBGN
    [all...]
SystemZInstrInfo.h 178 void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/AsmParser/
PPCAsmParser.cpp 1508 std::string NewOpcode;
1510 NewOpcode = std::string(Name);
1511 NewOpcode += '+';
1512 Name = NewOpcode;
1515 NewOpcode = std::string(Name);
1516 NewOpcode += '-';
1517 Name = NewOpcode;
1523 if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1531 if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ExpandPseudoInsts.cpp 468 int NewOpcode;
470 if ((NewOpcode = AArch64::getSVERevInstr(Opcode)) != -1)
471 Opcode = NewOpcode;
473 else if ((NewOpcode = AArch64::getSVENonRevInstr(Opcode)) != -1)
474 Opcode = NewOpcode;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Disassembler/
AMDGPUDisassembler.cpp 758 int NewOpcode =
760 if (NewOpcode == -1)
766 auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass;
789 auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass;
796 MI.setOpcode(NewOpcode);
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
InstructionSelectorImpl.h 827 int64_t NewOpcode = MatchTable[CurrentIdx++];
833 OutMIs[NewInsnID]->setDesc(TII.get(NewOpcode));
837 << NewOpcode << ")\n");
LegalizerHelper.h 250 void changeOpcode(MachineInstr &MI, unsigned NewOpcode);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsDelaySlotFiller.cpp 565 unsigned NewOpcode = TII->getEquivalentCompactForm(Branch);
566 Branch = TII->genInstrWithNewOpc(NewOpcode, Branch);
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelDAGToDAG.cpp 6857 unsigned NewOpcode;
6861 case PPC::RLWINM: NewOpcode = PPC::RLWINM8; break;
6862 case PPC::RLWNM: NewOpcode = PPC::RLWNM8; break;
6863 case PPC::SLW: NewOpcode = PPC::SLW8; break;
6864 case PPC::SRW: NewOpcode = PPC::SRW8; break;
6865 case PPC::LI: NewOpcode = PPC::LI8; break;
6866 case PPC::LIS: NewOpcode = PPC::LIS8; break;
6867 case PPC::LHBRX: NewOpcode = PPC::LHBRX8; break;
6868 case PPC::LWBRX: NewOpcode = PPC::LWBRX8; break;
6869 case PPC::CNTLZW: NewOpcode = PPC::CNTLZW8; break
    [all...]
PPCAsmPrinter.cpp 1313 unsigned NewOpcode =
1317 EmitToStreamer(*OutStreamer, MCInstBuilder(NewOpcode)
1327 unsigned NewOpcode =
1333 EmitToStreamer(*OutStreamer, MCInstBuilder(NewOpcode)

Completed in 45 milliseconds

1 2