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    Searched refs:NextReg (Results 1 - 6 of 6) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMFrameLowering.cpp 1338 unsigned NextReg = ARM::D8;
1343 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1349 .addReg(NextReg)
1352 NextReg += 4;
1358 unsigned R4BaseReg = NextReg;
1362 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1368 .addReg(NextReg)
1371 NextReg += 4;
1377 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1385 NextReg += 2
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCMIPeephole.cpp 1111 unsigned NextReg = SrcReg;
1114 NextReg = getIncomingRegForBlock(Inst, BB1);
1119 NextReg = Inst->getOperand(1).getReg();
1120 if (NextReg == SrcReg || !Register::isVirtualRegister(NextReg))
1122 SrcReg = NextReg;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64FrameLowering.cpp 2298 unsigned NextReg = CSI[i + RegInc].getReg();
2302 if (AArch64::GPR64RegClass.contains(NextReg) &&
2303 !invalidateRegisterPairing(RPI.Reg1, NextReg, IsWindows,
2305 RPI.Reg2 = NextReg;
2308 if (AArch64::FPR64RegClass.contains(NextReg) &&
2309 !invalidateWindowsRegisterPairing(RPI.Reg1, NextReg, NeedsWinCFI,
2311 RPI.Reg2 = NextReg;
2314 if (AArch64::FPR128RegClass.contains(NextReg))
2315 RPI.Reg2 = NextReg;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64InstructionSelector.cpp 1256 Register NextReg = MI->getOperand(1).getReg();
1258 if (!NextReg.isValid() || !MRI.hasOneNonDBGUse(NextReg))
1261 // NextReg is worth folding. Keep looking.
1262 Reg = NextReg;
1306 Register NextReg;
1314 NextReg = TestReg;
1320 NextReg = TestReg;
1327 NextReg = TestReg;
1335 NextReg = TestReg
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/
AMDGPUAsmParser.cpp 2584 unsigned NextReg, NextRegNum, NextRegWidth;
2587 if (!ParseAMDGPURegister(NextRegKind, NextReg,
2600 if (!AddNextRegisterToList(Reg, RegWidth, RegKind, NextReg, Loc))
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/
MipsAsmParser.cpp 3222 static unsigned nextReg(unsigned Reg) {
3451 if (loadImmediate(0, nextReg(FirstReg), Mips::NoRegister, true, false,
3488 TOut.emitRRI(Mips::LW, nextReg(FirstReg), TmpReg, 4, IDLoc, STI);
3533 TOut.emitRR(Mips::MTC1, nextReg(FirstReg), TmpReg, IDLoc, STI);
5285 unsigned SecondReg = nextReg(FirstReg);
5332 unsigned SecondReg = nextReg(FirstReg);
6141 int NextReg = nextReg(((MipsOperand &)*Operands[1]).getGPR32Reg());
6142 Inst.addOperand(MCOperand::createReg(NextReg));

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