| /src/external/apache2/llvm/dist/llvm/include/llvm/MC/ |
| MCRegister.h | 41 static constexpr unsigned NoRegister = 0u;
66 assert(Val == NoRegister || isPhysicalRegister(Val));
74 bool isValid() const { return Reg != NoRegister; }
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyReplacePhysRegs.cpp | 79 for (unsigned PReg = WebAssembly::NoRegister + 1;
87 unsigned VReg = WebAssembly::NoRegister;
91 if (VReg == WebAssembly::NoRegister) {
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| Register.h | 121 assert(Reg == MCRegister::NoRegister ||
126 bool isValid() const { return Reg != MCRegister::NoRegister; }
|
| LiveRegMatrix.h | 140 MCRegister PhysReg = MCRegister::NoRegister);
|
| RegisterClassInfo.h | 114 /// overlaps PhysReg, or NoRegister if Reg doesn't overlap a
119 return MCRegister::NoRegister;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| R600RegisterInfo.cpp | 68 static const MCPhysReg CalleeSavedReg = R600::NoRegister;
76 return R600::NoRegister;
|
| SIMachineFunctionInfo.cpp | 313 if (LaneVGPR == AMDGPU::NoRegister) {
379 Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister);
625 this->VGPRReservedForSGPRSpill = AMDGPU::NoRegister;
|
| SIOptimizeExecMasking.cpp | 69 return AMDGPU::NoRegister;
131 return AMDGPU::NoRegister;
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| SIRegisterInfo.cpp | 88 Register TmpVGPR = AMDGPU::NoRegister;
94 Register SavedExecReg = AMDGPU::NoRegister;
357 static const MCPhysReg NoCalleeSavedReg = AMDGPU::NoRegister;
394 // an immediate "0" which we represent by returning NoRegister.
542 if (ScratchRSrcReg != AMDGPU::NoRegister) {
928 if (Reg == AMDGPU::NoRegister)
1113 if (ScratchOffsetReg == AMDGPU::NoRegister) {
1124 if (IsFlat && SOffset == AMDGPU::NoRegister) {
1236 if (SOffset == AMDGPU::NoRegister) {
1252 if (!IsStore && TmpReg != AMDGPU::NoRegister) {
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| LVLGen.cpp | 50 // returns a register holding a vector length. NoRegister is returned when
57 return VE::NoRegister;
78 if (Reg != VE::NoRegister) {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86LoadValueInjectionRetHardening.cpp | 83 if (ClobberReg != X86::NoRegister) {
|
| X86AvoidStoreForwardingBlocks.cpp | 320 if (!((Base.isReg() && Base.getReg() != X86::NoRegister) || Base.isFI()))
326 if (!(Index.isReg() && Index.getReg() == X86::NoRegister))
328 if (!(Segment.isReg() && Segment.getReg() == X86::NoRegister))
403 .addReg(X86::NoRegister)
405 .addReg(X86::NoRegister)
422 .addReg(X86::NoRegister)
424 .addReg(X86::NoRegister)
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| X86CallFrameOptimization.cpp | 431 (I->getOperand(X86::AddrIndexReg).getReg() != X86::NoRegister) ||
432 (I->getOperand(X86::AddrSegmentReg).getReg() != X86::NoRegister) ||
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| MVETailPredUtils.h | 97 MIB.addReg(ARM::NoRegister);
105 MIB.addReg(ARM::NoRegister);
162 MIB.addReg(ARM::NoRegister);
|
| Thumb1FrameLowering.cpp | 79 if (ScratchReg == ARM::NoRegister)
184 ARM::NoRegister, MachineInstr::FrameSetup);
197 ARM::NoRegister, MachineInstr::FrameSetup);
378 unsigned ScratchRegister = ARM::NoRegister;
493 NumBytes - ArgRegsSaveSize, ARM::NoRegister,
532 unsigned ScratchRegister = ARM::NoRegister;
737 ArgRegsSaveSize + 4, ARM::NoRegister,
780 ARM::NoRegister, MachineInstr::NoFlags);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/AsmParser/ |
| AVRAsmParser.cpp | 344 if (RegNum == AVR::NoRegister) {
347 if (RegNum == AVR::NoRegister) {
357 if (RegNum == AVR::NoRegister)
364 int RegNum = AVR::NoRegister;
378 if (RegNum == AVR::NoRegister && RestoreOnFailure) {
392 if (RegNo == AVR::NoRegister)
567 if (RegNo == AVR::NoRegister)
593 return (RegNo == AVR::NoRegister);
603 if (RegNo == AVR::NoRegister)
726 if (RegNum != AVR::NoRegister) {
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/Disassembler/ |
| VEDisassembler.cpp | 118 VE::USRCC, VE::PSW, VE::SAR, VE::NoRegister,
119 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::PMMR,
121 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::NoRegister,
170 unsigned Reg = VE::NoRegister;
207 if (Reg == VE::NoRegister)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/AsmParser/ |
| VEAsmParser.cpp | 132 VE::USRCC, VE::PSW, VE::SAR, VE::NoRegister,
133 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::PMMR,
135 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::NoRegister,
683 if (regIdx > 31 || MISCRegs[regIdx] == VE::NoRegister)
812 if (RegNum == VE::NoRegister) {
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/Disassembler/ |
| HexagonDisassembler.cpp | 496 assert(Producer != Hexagon::NoRegister);
511 assert(Producer != Hexagon::NoRegister);
674 static_assert(NoRegister == 0, "Expecting NoRegister to be 0");
675 if (CtrlRegDecoderTable[RegNo] == NoRegister)
702 static_assert(NoRegister == 0, "Expecting NoRegister to be 0");
703 if (CtrlReg64DecoderTable[RegNo] == NoRegister)
781 if (GuestRegDecoderTable[RegNo] == Hexagon::NoRegister)
807 if (GuestReg64DecoderTable[RegNo] == Hexagon::NoRegister)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCTLSDynamicCall.cpp | 83 Register InReg = PPC::NoRegister;
161 assert(InReg != PPC::NoRegister && "Operand must be a register");
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| InterferenceCache.h | 105 PhysReg = MCRegister::NoRegister;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/MCTargetDesc/ |
| AVRInstPrinter.cpp | 95 RegNum = (RegLoNum != AVR::NoRegister) ? RegLoNum : RegNum;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/MCTargetDesc/ |
| RISCVInstPrinter.cpp | 182 if (MO.getReg() == RISCV::NoRegister)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCChecker.cpp | 35 HexagonMCChecker::Unconditional(Hexagon::NoRegister, false);
91 unsigned PredReg = Hexagon::NoRegister;
132 unsigned R = MCI.getOperand(i).getReg(), S = Hexagon::NoRegister;
445 if (std::get<2>(Producer).Register != Hexagon::NoRegister &&
547 (ProducerPredicate.Register == Hexagon::NoRegister ||
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCTargetDesc.cpp | 77 for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
614 default: return X86::NoRegister;
638 default: return X86::NoRegister;
675 default: return X86::NoRegister;
711 default: return X86::NoRegister;
786 assert(Res != X86::NoRegister && "Unexpected register or VT");
|
