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    Searched refs:NotOpc (Results 1 - 3 of 3) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIRegisterInfo.cpp 108 unsigned NotOpc;
125 NotOpc = AMDGPU::S_NOT_B32;
129 NotOpc = AMDGPU::S_NOT_B64;
204 auto I = BuildMI(MBB, MI, DL, TII.get(NotOpc), ExecReg).addReg(ExecReg);
238 auto I = BuildMI(MBB, MI, DL, TII.get(NotOpc), ExecReg).addReg(ExecReg);
264 BuildMI(MBB, MI, DL, TII.get(NotOpc), ExecReg).addReg(ExecReg);
266 BuildMI(MBB, MI, DL, TII.get(NotOpc), ExecReg).addReg(ExecReg);
SIInstrInfo.cpp 1757 unsigned NotOpc = ST.isWave32() ? AMDGPU::S_NOT_B32 : AMDGPU::S_NOT_B64;
1759 auto FirstNot = BuildMI(MBB, MI, DL, get(NotOpc), Exec).addReg(Exec);
1763 BuildMI(MBB, MI, DL, get(NotOpc), Exec)
1769 unsigned NotOpc = ST.isWave32() ? AMDGPU::S_NOT_B32 : AMDGPU::S_NOT_B64;
1771 auto FirstNot = BuildMI(MBB, MI, DL, get(NotOpc), Exec).addReg(Exec);
1777 BuildMI(MBB, MI, DL, get(NotOpc), Exec)
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64InstructionSelector.cpp 3607 unsigned NotOpc = Pred == ICmpInst::ICMP_NE ? AArch64::NOTv8i8 : 0;
3609 NotOpc = NotOpc ? AArch64::NOTv16i8 : 0;
3618 if (NotOpc) {
3619 Cmp = MIB.buildInstr(NotOpc, {DstReg}, {Cmp});

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