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  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
StackMaps.h 174 NumDefs = MI->getNumDefs();
178 unsigned getIDPos() const { return NumDefs + IDPos; }
181 unsigned getNBytesPos() const { return NumDefs + NBytesPos; }
184 unsigned getNCallArgsPos() const { return NumDefs + NCallArgsPos; }
189 return MI->getOperand(NumDefs + NCallArgsPos).getImm() + MetaEnd + NumDefs;
204 uint64_t getID() const { return MI->getOperand(NumDefs + IDPos).getImm(); }
208 return MI->getOperand(NumDefs + NBytesPos).getImm();
213 return MI->getOperand(NumDefs + CallTargetPos);
248 unsigned NumDefs;
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  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
LegalizationArtifactCombiner.h 364 const unsigned NumDefs = MI.getNumOperands() - 1;
369 const LLT SrcTy = MRI.getType(MI.getOperand(NumDefs).getReg());
386 DestTy.isVector() ? CastSrcTy.getNumElements() / NumDefs : 1;
396 for (unsigned I = 0; I != NumDefs; ++I) {
427 if (Idx < NumDefs)
541 unsigned NumDefs = MI.getNumOperands() - 1;
542 Register SrcReg = MI.getOperand(NumDefs).getReg();
547 LLT OpTy = MRI.getType(MI.getOperand(NumDefs).getReg());
585 for (unsigned I = 0; I != NumDefs; ++I) {
587 replaceRegOrBuildCopy(Def, NewUnmerge.getReg(SrcDefIdx * NumDefs + I)
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  /src/external/apache2/llvm/dist/llvm/lib/MC/
MCInstrDesc.cpp 44 for (int i = 0, e = NumDefs; i != e; ++i)
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/GlobalISel/
GIMatchDagOperands.cpp 81 i < I.Operands.NumDefs);
92 NewValue->add(I.Operands[i].Name, i, i < I.Operands.NumDefs);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/AsmPrinter/
AsmPrinterInlineAsm.cpp 461 unsigned NumDefs = 0;
462 for (; MI->getOperand(NumDefs).isReg() && MI->getOperand(NumDefs).isDef();
463 ++NumDefs)
464 assert(NumDefs != MI->getNumOperands()-2 && "No asm string?");
466 assert(MI->getOperand(NumDefs).isSymbol() && "No asm string?");
469 const char *AsmStr = MI->getOperand(NumDefs).getSymbolName();
  /src/external/apache2/llvm/dist/llvm/include/llvm/MC/
MCInstrDesc.h 199 unsigned char NumDefs; // Num of args that are definitions
243 unsigned getNumDefs() const { return NumDefs; }
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
CodeGenInstruction.cpp 43 NumDefs = OutDI->getNumArgs();
63 if (i < NumDefs) {
67 ArgInit = InDI->getArg(i-NumDefs);
68 ArgName = InDI->getArgNameStr(i-NumDefs);
113 if (i < NumDefs)
144 --NumDefs;
294 if (DestOp.first >= Ops.NumDefs)
298 if (SrcOp.first < Ops.NumDefs)
CodeGenInstruction.h 142 /// NumDefs - Number of def operands declared, this is the number of
145 unsigned NumDefs;
InstrDocsEmitter.cpp 152 bool IsDef = i < II->Operands.NumDefs;
GlobalISelEmitter.cpp 4711 const unsigned NumDefs = DstI->Operands.NumDefs;
4712 if (NumDefs == 0)
4719 if (Dst->getExtTypes().size() < NumDefs)
4724 for (unsigned I = 1; I < NumDefs; ++I) {
4835 unsigned DstINumUses = OrigDstI->Operands.size() - OrigDstI->Operands.NumDefs;
4843 unsigned NumResults = OrigDstI->Operands.NumDefs;
4870 unsigned InstOpNo = DstI->Operands.NumDefs + I;
5001 if (Inst.Operands.NumDefs > 1)
5191 if (DstI.Operands.NumDefs < Src->getExtTypes().size()
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  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
InstrEmitter.cpp 904 unsigned NumDefs = II.getNumDefs();
915 NumDefs = NumResults;
919 NumDefs = NumResults;
924 countOperands(Node, II.getNumOperands() - NumDefs, NumImpUses);
927 bool HasPhysRegOuts = NumResults > NumDefs &&
988 bool HasOptPRefs = NumDefs > NumResults;
991 unsigned NumSkip = HasOptPRefs ? NumDefs - NumResults : 0;
993 AddOperand(MIB, Node->getOperand(i), i-NumSkip+NumDefs, &II,
1030 for (unsigned i = NumDefs; i < NumResults; ++i) {
1031 Register Reg = II.getImplicitDefs()[i - NumDefs];
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ScheduleDAGRRList.cpp 2117 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
2118 for (unsigned i = 0; i != NumDefs; ++i) {
2163 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
2164 for (unsigned i = 0; i != NumDefs; ++i) {
2292 unsigned NumDefs = TII->get(PN->getMachineOpcode()).getNumDefs();
2293 for (unsigned i = 0; i != NumDefs; ++i) {
2309 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
2310 for (unsigned i = NumDefs, e = N->getNumValues(); i != e; ++i) {
2880 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
2892 for (unsigned i = NumDefs, e = N->getNumValues(); i != e; ++i)
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  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
FixupStatepointCallerSaved.cpp 482 unsigned NumDefs = MI.getNumDefs();
483 for (unsigned I = 0; I < NumDefs; ++I) {
515 for (unsigned I = NumDefs; I < MI.getNumOperands(); ++I) {
530 assert(OldDef < NumDefs);
ImplicitNullChecks.cpp 715 unsigned NumDefs = MI->getDesc().getNumDefs();
716 assert(NumDefs <= 1 && "other cases unhandled!");
719 if (NumDefs != 0) {
721 assert(NumDefs == 1 && "expected exactly one def!");
MachineCSE.cpp 610 unsigned NumDefs = MI->getNumDefs();
612 for (unsigned i = 0, e = MI->getNumOperands(); NumDefs && i != e; ++i) {
630 --NumDefs;
655 --NumDefs;
TargetInstrInfo.cpp 499 unsigned NumDefs = 0;
501 std::tie(NumDefs, StartIdx) = TII.getPatchpointUnfoldableRange(MI);
508 if (Op < NumDefs) {
550 assert(TiedTo < NumDefs && "Bad tied operand");
MachineInstr.cpp 746 unsigned NumDefs = MCID->getNumDefs();
748 return NumDefs;
750 for (unsigned I = NumDefs, E = getNumOperands(); I != E; ++I) {
754 ++NumDefs;
756 return NumDefs;
1154 unsigned NumDefs = getNumDefs();
1155 for (unsigned CurDefIdx = 0; CurDefIdx < NumDefs; ++CurDefIdx) {
MachineLICM.cpp 1071 unsigned NumDefs = MI.getDesc().getNumDefs();
1072 for (unsigned i = 0, e = MI.getNumOperands(); NumDefs && i != e; ++i) {
1076 --NumDefs;
PeepholeOptimizer.cpp 871 unsigned NumDefs; ///< Number of defs in the bitcast.
875 NumDefs = MI.getDesc().getNumDefs();
885 if (CurrentSrcIdx == NumDefs)
890 if (CurrentSrcIdx == NumDefs)
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/
X86MCTargetDesc.cpp 419 unsigned NumDefs = Desc.getNumDefs();
421 assert(Mask.getBitWidth() == NumDefs + NumImplicitDefs &&
452 for (unsigned I = 0, E = NumDefs; I < E; ++I) {
461 Mask.setBit(NumDefs + I);
X86BaseInfo.h 1047 unsigned NumDefs = Desc.getNumDefs();
1049 switch (NumDefs) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
BTFDebug.cpp 1067 unsigned NumDefs = 0;
1068 for (; MI->getOperand(NumDefs).isReg() && MI->getOperand(NumDefs).isDef();
1069 ++NumDefs)
1073 const char *AsmStr = MI->getOperand(NumDefs).getSymbolName();
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonBitTracker.cpp 190 unsigned NumDefs = 0;
196 NumDefs++;
200 if (NumDefs == 0)
HexagonInstrInfo.cpp 4493 unsigned NumDefs = 0;
4494 for (; MI.getOperand(NumDefs).isReg() && MI.getOperand(NumDefs).isDef();
4495 ++NumDefs)
4496 assert(NumDefs != MI.getNumOperands()-2 && "No asm string?");
4498 assert(MI.getOperand(NumDefs).isSymbol() && "No asm string?");
4500 const char *AsmStr = MI.getOperand(NumDefs).getSymbolName();
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86InstructionSelector.cpp 1290 unsigned NumDefs = I.getNumOperands() - 1;
1291 Register SrcReg = I.getOperand(NumDefs).getReg();
1294 for (unsigned Idx = 0; Idx < NumDefs; ++Idx) {

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