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    Searched refs:NumRegs (Results 1 - 25 of 61) sorted by relevancy

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  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
RegisterClassInfo.cpp 98 unsigned NumRegs = RC->getNumRegs();
101 RCI.Order.reset(new MCPhysReg[NumRegs]);
131 RCI.NumRegs = N + CSRAlias.size();
132 assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
145 if (StressRA && RCI.NumRegs > StressRA)
146 RCI.NumRegs = StressRA;
151 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)
159 for (unsigned I = 0; I != RCI.NumRegs; ++I)
ExecutionDomainFix.cpp 71 assert(unsigned(rx) < NumRegs && "Invalid index");
82 assert(unsigned(rx) < NumRegs && "Invalid index");
92 assert(unsigned(rx) < NumRegs && "Invalid index");
122 for (unsigned rx = 0; rx != NumRegs; ++rx)
144 for (unsigned rx = 0; rx != NumRegs; ++rx) {
160 LiveRegs.assign(NumRegs, nullptr);
178 for (unsigned rx = 0; rx != NumRegs; ++rx) {
420 assert(NumRegs == RC->getNumRegs() && "Bad regclass");
CFIInstrInserter.cpp 156 unsigned NumRegs = TRI.getNumRegs();
166 MBBInfo.IncomingCSRSaved.resize(NumRegs);
167 MBBInfo.OutgoingCSRSaved.resize(NumRegs);
186 unsigned NumRegs = TRI.getNumRegs();
187 BitVector CSRSaved(NumRegs), CSRRestored(NumRegs);
LiveVariables.cpp 424 for (unsigned Reg = 1, NumRegs = TRI->getNumRegs(); Reg != NumRegs; ++Reg) {
562 void LiveVariables::runOnBlock(MachineBasicBlock *MBB, const unsigned NumRegs) {
610 for (unsigned i = 0; i != NumRegs; ++i)
620 const unsigned NumRegs = TRI->getNumRegs();
621 PhysRegDef.assign(NumRegs, nullptr);
622 PhysRegUse.assign(NumRegs, nullptr);
642 runOnBlock(MBB, NumRegs);
644 PhysRegDef.assign(NumRegs, nullptr);
645 PhysRegUse.assign(NumRegs, nullptr)
    [all...]
RDFRegisters.cpp 204 unsigned NumRegs = TRI.getNumRegs();
208 for (unsigned w = 0, nw = NumRegs/32; w != nw; ++w) {
219 unsigned TailRegs = NumRegs % 32;
222 unsigned TW = NumRegs / 32;
VirtRegMap.cpp 78 unsigned NumRegs = MF->getRegInfo().getNumVirtRegs();
79 Virt2PhysMap.resize(NumRegs);
80 Virt2StackSlotMap.resize(NumRegs);
81 Virt2SplitMap.resize(NumRegs);
MachineRegisterInfo.cpp 48 unsigned NumRegs = getTargetRegisterInfo()->getNumRegs();
51 UsedPhysRegMask.resize(NumRegs);
52 PhysRegUseDefLists.reset(new MachineOperand*[NumRegs]());
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
RegisterClassInfo.h 33 unsigned NumRegs = 0;
42 return makeArrayRef(Order.get(), NumRegs);
93 return get(RC).NumRegs;
ExecutionDomainFix.h 125 const unsigned NumRegs;
140 : MachineFunctionPass(PassID), RC(&RC), NumRegs(RC.getNumRegs()) {}
TargetRegisterInfo.h 352 unsigned NumRegs = getNumRegs();
355 return makeArrayRef(&InfoDesc->CostPerUse[Idx * NumRegs], NumRegs);
LiveVariables.h 179 void runOnBlock(MachineBasicBlock *MBB, unsigned NumRegs);
MachineOperand.h 636 static unsigned getRegMaskSize(unsigned NumRegs) {
637 return (NumRegs + 31) / 32;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
GCNNSAReassign.cpp 86 bool canAssign(unsigned StartReg, unsigned NumRegs) const;
109 unsigned NumRegs = Intervals.size();
111 for (unsigned N = 0; N < NumRegs; ++N)
115 for (unsigned N = 0; N < NumRegs; ++N)
119 for (unsigned N = 0; N < NumRegs; ++N)
125 bool GCNNSAReassign::canAssign(unsigned StartReg, unsigned NumRegs) const {
126 for (unsigned N = 0; N < NumRegs; ++N) {
142 unsigned NumRegs = Intervals.size();
144 if (NumRegs > MaxNumVGPRs)
146 unsigned MaxReg = MaxNumVGPRs - NumRegs + AMDGPU::VGPR0
    [all...]
  /src/external/apache2/llvm/dist/llvm/include/llvm/MCA/HardwareUnits/
RegisterFile.h 229 void initialize(const MCSchedModel &SM, unsigned NumRegs);
233 unsigned NumRegs = 0);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
InlineAsmLowering.cpp 112 // Initialize NumRegs.
113 unsigned NumRegs = 1;
115 NumRegs =
134 for (; NumRegs; --NumRegs, ++I) {
552 unsigned NumRegs = OpInfo.Regs.size();
554 assert(NumRegs == SourceRegs.size() &&
558 if (NumRegs > 1) {
564 unsigned Flag = InlineAsm::getFlagWord(InlineAsm::Kind_RegUse, NumRegs);
579 unsigned NumRegs = OpInfo.Regs.size()
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/MCA/HardwareUnits/
RegisterFile.cpp 63 unsigned NumRegs)
67 initialize(SM, NumRegs);
70 void RegisterFile::initialize(const MCSchedModel &SM, unsigned NumRegs) {
73 // register file is set equal to `NumRegs`. A value of zero for `NumRegs`
75 RegisterFiles.emplace_back(NumRegs);
595 unsigned NumRegs = NumPhysRegs[I];
596 if (!NumRegs)
606 if (RMT.NumPhysRegs < NumRegs) {
618 NumRegs = RMT.NumPhysRegs
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyMachineFunctionInfo.cpp 42 unsigned NumRegs = TLI.getNumRegisters(F.getContext(), VT);
44 for (unsigned I = 0; I != NumRegs; ++I)
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMSelectionDAGInfo.cpp 231 unsigned NumRegs = NextEmittedNumMemOps - EmittedNumMemOps;
234 DAG.getConstant(NumRegs, dl, MVT::i32));
238 DstPtrInfo = DstPtrInfo.getWithOffset(NumRegs * VTSize);
239 SrcPtrInfo = SrcPtrInfo.getWithOffset(NumRegs * VTSize);
ARMExpandPseudoInsts.cpp 161 uint8_t NumRegs; // D registers loaded or stored
535 unsigned NumRegs = TableEntry->NumRegs;
561 if (NumRegs > 1 && TableEntry->copyAllListRegs)
563 if (NumRegs > 2 && TableEntry->copyAllListRegs)
565 if (NumRegs > 3 && TableEntry->copyAllListRegs)
646 unsigned NumRegs = TableEntry->NumRegs;
689 if (NumRegs > 1 && TableEntry->copyAllListRegs)
691 if (NumRegs > 2 && TableEntry->copyAllListRegs
    [all...]
  /src/external/apache2/llvm/dist/llvm/include/llvm/MC/
MCRegisterInfo.h 157 unsigned NumRegs; // Number of entries in the array
367 NumRegs = NR;
447 assert(RegNo < NumRegs &&
492 return NumRegs;
554 assert(RegNo < NumRegs &&
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
SparcISelDAGToDAG.cpp 200 unsigned NumRegs = InlineAsm::getNumOperandRegisters(Flag);
201 if (NumRegs)
218 || NumRegs != 2)
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86CallingConv.cpp 243 static const unsigned NumRegs = sizeof(RegList) / sizeof(RegList[0]);
278 bool UseRegs = PendingMembers.size() <= std::min(2U, NumRegs - FirstFree);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/LiveDebugValues/
InstrRefBasedImpl.cpp 437 /// number is the index in SpillLocs minus one plus NumRegs.
445 unsigned NumRegs;
495 NumRegs = TRI.getNumRegs();
497 LocIDToLocIdx.resize(NumRegs, LocIdx::MakeIllegalLoc());
498 assert(NumRegs < (1u << NUM_LOC_BITS)); // Detect bit packing failure
513 return (isSpill) ? RegOrSpill.id() + NumRegs - 1 : RegOrSpill.id();
561 LocIDToLocIdx.resize(NumRegs, LocIdx::MakeIllegalLoc());
654 if (ID < NumRegs && ID != SP && MO->clobbersPhysReg(ID))
708 return LocIdxToLocID[Idx] >= NumRegs;
726 if (ID >= NumRegs)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonBlockRanges.cpp 474 unsigned NumRegs = TRI.getNumRegs();
475 BitVector Visited(NumRegs);
476 for (unsigned R = 1; R < NumRegs; ++R) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/
AArch64InstPrinter.cpp 1281 unsigned NumRegs = 1;
1285 NumRegs = 2;
1289 NumRegs = 3;
1293 NumRegs = 4;
1311 for (unsigned i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg)) {
1317 if (i + 1 != NumRegs)

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