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    Searched refs:NumSubRegs (Results 1 - 3 of 3) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIRegisterInfo.cpp 81 unsigned NumSubRegs;
120 NumSubRegs = SplitParts.empty() ? 1 : SplitParts.size();
140 Data.NumVGPRs = (NumSubRegs + (Data.PerVGPR - 1)) / Data.PerVGPR;
141 Data.VGPRLanes = (1LL << std::min(Data.PerVGPR, NumSubRegs)) - 1LL;
1049 unsigned NumSubRegs = RegWidth / EltSize;
1050 unsigned Size = NumSubRegs * EltSize;
1135 for (unsigned i = 0, e = NumSubRegs + NumRemSubRegs, RegOffset = 0; i != e;
1137 if (i == NumSubRegs) {
1320 for (unsigned i = 0, e = SB.NumSubRegs; i < e; ++i) {
1322 SB.NumSubRegs ==
    [all...]
SIInstrInfo.cpp 5153 unsigned NumSubRegs = RegSize / 32;
5154 assert(NumSubRegs % 2 == 0 && NumSubRegs <= 32 && "Unhandled register size");
5156 for (unsigned Idx = 0; Idx < NumSubRegs; Idx += 2) {
5184 if (NumSubRegs <= 2)
  /src/external/apache2/llvm/dist/llvm/lib/Target/VE/
VEInstrInfo.cpp 329 const MCInstrDesc &MCID, unsigned int NumSubRegs,
334 for (unsigned Idx = 0; Idx != NumSubRegs; ++Idx) {
394 unsigned int NumSubRegs = 2;
396 NumSubRegs, SubRegIdx, &getRegisterInfo());
400 unsigned int NumSubRegs = 2;
402 NumSubRegs, SubRegIdx, &getRegisterInfo());

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