| /src/external/bsd/pcc/dist/pcc/arch/sparc64/ |
| order.c | 110 static int ret[] = { O0, O1, O2, O3, O4, O5, O6, O7, -1 };
|
| macdefs.h | 135 #define O7 14
|
| /src/external/gpl3/gdb/dist/gdb/stubs/ |
| sparc-stub.c | 111 O0, O1, O2, O3, O4, O5, SP, O7,
626 *ptr++ = hexchars[O7 >> 4];
627 *ptr++ = hexchars[O7 & 0xf];
629 ptr = mem2hex((char *)®isters[O7], ptr, 4, 0);
|
| /src/external/gpl3/gdb.old/dist/gdb/stubs/ |
| sparc-stub.c | 111 O0, O1, O2, O3, O4, O5, SP, O7,
626 *ptr++ = hexchars[O7 >> 4];
627 *ptr++ = hexchars[O7 & 0xf];
629 ptr = mem2hex((char *)®isters[O7], ptr, 4, 0);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/MCTargetDesc/ |
| SparcMCTargetDesc.cpp | 63 InitSparcMCRegisterInfo(X, SP::O7);
|
| SparcInstPrinter.cpp | 74 case SP::O7: O << "\tretl"; return true;
79 case SP::O7: // call $addr
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| SparcAsmPrinter.cpp | 176 assert(MO.getReg() != SP::O7 &&
177 "%o7 is assigned as destination for getpcx!");
211 // Use register %o7 to load the lower 32 bits.
212 MCOperand RegO7 = MCOperand::createReg(SP::O7);
226 MCOperand RegO7 = MCOperand::createReg(SP::O7);
234 // add <MO>, %o7, <MO>
|
| SparcRegisterInfo.cpp | 36 SparcRegisterInfo::SparcRegisterInfo() : SparcGenRegisterInfo(SP::O7) {}
|
| DelaySlotFiller.cpp | 293 // Call defines o7, which is visible to the instruction in delay slot.
294 RegDefs.insert(SP::O7);
|
| SparcFrameLowering.cpp | 165 unsigned regOutRA = RegInfo.getDwarfRegNum(SP::O7, true);
|
| SparcISelLowering.cpp | 187 static_assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7,
1024 .Case("o4", SP::O4).Case("o5", SP::O5).Case("o6", SP::O6).Case("o7", SP::O7)
3300 // r8-r15 -> o0-o7
|
| /src/external/gpl3/binutils/dist/gas/config/ |
| tc-sparc.c | 3587 #define O7 15
3600 arithmetic instruction with rd == %o7
3601 where rs1 != %o7 and rs2 if it is register != %o7
3612 || ((delay & RD (~0)) != RD (O7))))
3614 if ((delay & RS1 (~0)) == RS1 (O7)
3616 && (delay & RS2 (~0)) == RS2 (O7)))
3635 == (INSN_OR | RD (O7) | RS2 (G0))))
3645 != (INSN_OR | RS1 (O7) | RS2 (G0)))
3648 or %o7, %g0, %r
[all...] |
| /src/external/gpl3/binutils.old/dist/gas/config/ |
| tc-sparc.c | 3586 #define O7 15
3599 arithmetic instruction with rd == %o7
3600 where rs1 != %o7 and rs2 if it is register != %o7
3611 || ((delay & RD (~0)) != RD (O7))))
3613 if ((delay & RS1 (~0)) == RS1 (O7)
3615 && (delay & RS2 (~0)) == RS2 (O7)))
3634 == (INSN_OR | RD (O7) | RS2 (G0))))
3644 != (INSN_OR | RS1 (O7) | RS2 (G0)))
3647 or %o7, %g0, %r
[all...] |
| /src/external/gpl3/binutils/dist/bfd/ |
| elfxx-sparc.c | 913 /* mov %o7,%g5
916 ldx [%o7+P],%g1
917 jmpl %o7+%g1,%g1
918 mov %g5,%o7 */
3992 #define O7 15
4005 arithmetic instruction with rd == %o7
4006 where rs1 != %o7 and rs2 if it is register != %o7
4015 && (y & RD(~0)) == RD(O7)))
4016 && (y & RS1(~0)) != RS1(O7)
[all...] |
| /src/external/gpl3/binutils.old/dist/bfd/ |
| elfxx-sparc.c | 916 /* mov %o7,%g5
919 ldx [%o7+P],%g1
920 jmpl %o7+%g1,%g1
921 mov %g5,%o7 */
3995 #define O7 15
4008 arithmetic instruction with rd == %o7
4009 where rs1 != %o7 and rs2 if it is register != %o7
4018 && (y & RD(~0)) == RD(O7)))
4019 && (y & RS1(~0)) != RS1(O7)
[all...] |
| /src/external/gpl3/gdb.old/dist/bfd/ |
| elfxx-sparc.c | 916 /* mov %o7,%g5
919 ldx [%o7+P],%g1
920 jmpl %o7+%g1,%g1
921 mov %g5,%o7 */
3966 #define O7 15
3979 arithmetic instruction with rd == %o7
3980 where rs1 != %o7 and rs2 if it is register != %o7
3989 && (y & RD(~0)) == RD(O7)))
3990 && (y & RS1(~0)) != RS1(O7)
[all...] |
| /src/external/gpl3/gdb/dist/bfd/ |
| elfxx-sparc.c | 916 /* mov %o7,%g5
919 ldx [%o7+P],%g1
920 jmpl %o7+%g1,%g1
921 mov %g5,%o7 */
3977 #define O7 15
3990 arithmetic instruction with rd == %o7
3991 where rs1 != %o7 and rs2 if it is register != %o7
4000 && (y & RD(~0)) == RD(O7)))
4001 && (y & RS1(~0)) != RS1(O7)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/AsmParser/ |
| SparcAsmParser.cpp | 139 Sparc::O4, Sparc::O5, Sparc::O6, Sparc::O7,
463 else if (Reg >= Sparc::O0 && Reg <= Sparc::O7)
1216 // %o0 - %o7
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/Disassembler/ |
| SparcDisassembler.cpp | 64 SP::O4, SP::O5, SP::O6, SP::O7,
|
