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    Searched refs:OP2 (Results 1 - 25 of 50) sorted by relevancy

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  /src/external/gpl3/gdb.old/dist/sim/pru/
pru.isa 27 OP2 = (IO ? IMM8 : RS2);
28 RD = RS1 + OP2;
29 CARRY = (((uint64_t) RS1 + (uint64_t) OP2) >> RD_WIDTH) & 1;
33 OP2 = (IO ? IMM8 : RS2);
34 RD = RS1 + OP2 + CARRY;
35 CARRY = (((uint64_t) RS1 + (uint64_t) OP2 + (uint64_t) CARRY)
40 OP2 = (IO ? IMM8 : RS2);
41 RD = RS1 - OP2;
42 CARRY = (((uint64_t) RS1 - (uint64_t) OP2) >> RD_WIDTH) & 1;
47 OP2 = (IO ? IMM8 : RS2)
    [all...]
  /src/external/gpl3/gdb/dist/sim/pru/
pru.isa 27 OP2 = (IO ? IMM8 : RS2);
28 RD = RS1 + OP2;
29 CARRY = (((uint64_t) RS1 + (uint64_t) OP2) >> RD_WIDTH) & 1;
33 OP2 = (IO ? IMM8 : RS2);
34 RD = RS1 + OP2 + CARRY;
35 CARRY = (((uint64_t) RS1 + (uint64_t) OP2 + (uint64_t) CARRY)
40 OP2 = (IO ? IMM8 : RS2);
41 RD = RS1 - OP2;
42 CARRY = (((uint64_t) RS1 - (uint64_t) OP2) >> RD_WIDTH) & 1;
47 OP2 = (IO ? IMM8 : RS2)
    [all...]
  /src/external/gpl3/gdb.old/dist/opcodes/
aarch64-tbl.h 33 #define OP2(a,b) {OPND(a), OPND(b)}
73 /* e.g. SYS #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>}. */
79 /* e.g. SYSL <Xt>, #<op1>, <Cn>, <Cm>, #<op2>. */
85 /* e.g. SYSP #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>, <Xt+1>}. */
3236 CORE_INSN ("ngc", 0x5a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF),
3238 CORE_INSN ("ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF),
3242 CORE_INSN ("cmn", 0x2b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_SUBCLASS_OTHER | F_ALIAS | F_SF),
3245 CORE_INSN ("cmp", 0x6b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_SUBCLASS_OTHER | F_ALIAS | F_SF),
3248 CORE_INSN ("mov", 0x11000000, 0x7ffffc00, addsub_imm, 0, OP2 (Rd_SP, Rn_SP), QL_I2SP, F_ARITH_MOV | F_ALIAS | F_SF),
3250 CORE_INSN ("cmn", 0x3100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_SUBCLASS_OTHER | F_ALIAS | F_SF)
    [all...]
cr16-opc.c 138 #define SHIFT_INST_A(NAME, OPC1, OPC2, SHIFT, OP1, OP2) \
140 {NAME, 1, OPC1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}}, \
142 {NAME, 1, OPC1+1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}},\
144 {NAME, 1, OPC2, 24, SHIFT_INS, {{regr,20}, {OP2,16}}}
150 #define SHIFT_INST_L(NAME, OPC1, OPC2, SHIFT, OP1, OP2) \
152 {NAME, 1, OPC1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}}, \
154 {NAME, 1, OPC2, 24, SHIFT_INS, {{regr,20}, {OP2,16}}}
  /src/crypto/external/apache2/openssl/dist/crypto/cast/
cast_local.h 103 #define E_CAST(n, key, L, R, OP1, OP2, OP3) \
111 + ((t >> C_2) & C_M)) OP2 \
126 #define E_CAST(n, key, L, R, OP1, OP2, OP3) \
139 t = (t OP2 * (CAST_LONG *)((unsigned char *)CAST_S_table1 + v)) & 0xffffffffL; \
148 #define E_CAST(n, key, L, R, OP1, OP2, OP3) \
157 L ^= (((((a OP2 b) & 0xffffffffL) OP3 c) & 0xffffffffL) OP1 d) & 0xffffffffL; \
  /src/external/cddl/osnet/dist/lib/libdtrace/common/
dt_grammar.y 35 #define OP2(op, l, r) dt_node_op2(op, l, r)
405 $$ = OP2(DT_TOK_LBRAC, $1, $3);
415 $$ = OP2(DT_TOK_DOT, $1, dt_node_ident($3));
418 $$ = OP2(DT_TOK_DOT, $1, dt_node_ident($3));
421 $$ = OP2(DT_TOK_DOT, $1, dt_node_ident($3));
424 $$ = OP2(DT_TOK_PTR, $1, dt_node_ident($3));
427 $$ = OP2(DT_TOK_PTR, $1, dt_node_ident($3));
430 $$ = OP2(DT_TOK_PTR, $1, dt_node_ident($3));
452 $$ = OP2(DT_TOK_XLATE, dt_node_type($3), $6);
481 $$ = OP2(DT_TOK_LPAR, dt_node_type($2), $4)
    [all...]
  /src/external/gpl3/binutils/dist/opcodes/
aarch64-tbl.h 33 #define OP2(a,b) {OPND(a), OPND(b)}
73 /* e.g. SYS #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>}. */
79 /* e.g. SYSL <Xt>, #<op1>, <Cn>, <Cm>, #<op2>. */
85 /* e.g. SYSP #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>, <Xt+1>}. */
3647 OP2 (MOPS_ADDR_Rd, MOPS_WB_Rn), QL_I2SAMEX, FLAGS, \
3694 CORE_INSN ("ngc", 0x5a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF),
3696 CORE_INSN ("ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF),
3700 CORE_INSN ("cmn", 0x2b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_SUBCLASS_OTHER | F_ALIAS | F_SF),
3703 CORE_INSN ("cmp", 0x6b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_SUBCLASS_OTHER | F_ALIAS | F_SF),
3706 CORE_INSN ("mov", 0x11000000, 0x7ffffc00, addsub_imm, 0, OP2 (Rd_SP, Rn_SP), QL_I2SP, F_ARITH_MOV | F_ALIAS | F_SF)
    [all...]
cr16-opc.c 138 #define SHIFT_INST_A(NAME, OPC1, OPC2, SHIFT, OP1, OP2) \
140 {NAME, 1, OPC1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}}, \
142 {NAME, 1, OPC1+1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}},\
144 {NAME, 1, OPC2, 24, SHIFT_INS, {{regr,20}, {OP2,16}}}
150 #define SHIFT_INST_L(NAME, OPC1, OPC2, SHIFT, OP1, OP2) \
152 {NAME, 1, OPC1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}}, \
154 {NAME, 1, OPC2, 24, SHIFT_INS, {{regr,20}, {OP2,16}}}
  /src/external/gpl3/binutils.old/dist/opcodes/
aarch64-tbl.h 33 #define OP2(a,b) {OPND(a), OPND(b)}
73 /* e.g. SYS #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>}. */
79 /* e.g. SYSL <Xt>, #<op1>, <Cn>, <Cm>, #<op2>. */
85 /* e.g. SYSP #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>, <Xt+1>}. */
3474 CORE_INSN ("ngc", 0x5a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF),
3476 CORE_INSN ("ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF),
3480 CORE_INSN ("cmn", 0x2b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_SUBCLASS_OTHER | F_ALIAS | F_SF),
3483 CORE_INSN ("cmp", 0x6b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_SUBCLASS_OTHER | F_ALIAS | F_SF),
3486 CORE_INSN ("mov", 0x11000000, 0x7ffffc00, addsub_imm, 0, OP2 (Rd_SP, Rn_SP), QL_I2SP, F_ARITH_MOV | F_ALIAS | F_SF),
3488 CORE_INSN ("cmn", 0x3100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_SUBCLASS_OTHER | F_ALIAS | F_SF)
    [all...]
cr16-opc.c 138 #define SHIFT_INST_A(NAME, OPC1, OPC2, SHIFT, OP1, OP2) \
140 {NAME, 1, OPC1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}}, \
142 {NAME, 1, OPC1+1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}},\
144 {NAME, 1, OPC2, 24, SHIFT_INS, {{regr,20}, {OP2,16}}}
150 #define SHIFT_INST_L(NAME, OPC1, OPC2, SHIFT, OP1, OP2) \
152 {NAME, 1, OPC1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}}, \
154 {NAME, 1, OPC2, 24, SHIFT_INS, {{regr,20}, {OP2,16}}}
  /src/external/gpl3/gdb/dist/opcodes/
aarch64-tbl.h 33 #define OP2(a,b) {OPND(a), OPND(b)}
73 /* e.g. SYS #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>}. */
79 /* e.g. SYSL <Xt>, #<op1>, <Cn>, <Cm>, #<op2>. */
85 /* e.g. SYSP #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>, <Xt+1>}. */
3474 CORE_INSN ("ngc", 0x5a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF),
3476 CORE_INSN ("ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF),
3480 CORE_INSN ("cmn", 0x2b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_SUBCLASS_OTHER | F_ALIAS | F_SF),
3483 CORE_INSN ("cmp", 0x6b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_SUBCLASS_OTHER | F_ALIAS | F_SF),
3486 CORE_INSN ("mov", 0x11000000, 0x7ffffc00, addsub_imm, 0, OP2 (Rd_SP, Rn_SP), QL_I2SP, F_ARITH_MOV | F_ALIAS | F_SF),
3488 CORE_INSN ("cmn", 0x3100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_SUBCLASS_OTHER | F_ALIAS | F_SF)
    [all...]
cr16-opc.c 138 #define SHIFT_INST_A(NAME, OPC1, OPC2, SHIFT, OP1, OP2) \
140 {NAME, 1, OPC1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}}, \
142 {NAME, 1, OPC1+1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}},\
144 {NAME, 1, OPC2, 24, SHIFT_INS, {{regr,20}, {OP2,16}}}
150 #define SHIFT_INST_L(NAME, OPC1, OPC2, SHIFT, OP1, OP2) \
152 {NAME, 1, OPC1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}}, \
154 {NAME, 1, OPC2, 24, SHIFT_INS, {{regr,20}, {OP2,16}}}
  /src/crypto/external/bsd/openssl/dist/crypto/cast/
cast_local.h 130 # define E_CAST(n,key,L,R,OP1,OP2,OP3) \
137 CAST_S_table0+((t>>C_2)&C_M)) OP2 \
146 # define E_CAST(n,key,L,R,OP1,OP2,OP3) \
159 t=(t OP2 *(CAST_LONG *)((unsigned char *)CAST_S_table1+v))&0xffffffffL;\
168 # define E_CAST(n,key,L,R,OP1,OP2,OP3) \
177 L^=(((((a OP2 b)&0xffffffffL) OP3 c)&0xffffffffL) OP1 d)&0xffffffffL; \
  /src/crypto/external/bsd/openssl.old/dist/crypto/cast/
cast_local.h 130 # define E_CAST(n,key,L,R,OP1,OP2,OP3) \
137 CAST_S_table0+((t>>C_2)&C_M)) OP2 \
146 # define E_CAST(n,key,L,R,OP1,OP2,OP3) \
159 t=(t OP2 *(CAST_LONG *)((unsigned char *)CAST_S_table1+v))&0xffffffffL;\
168 # define E_CAST(n,key,L,R,OP1,OP2,OP3) \
177 L^=(((((a OP2 b)&0xffffffffL) OP3 c)&0xffffffffL) OP1 d)&0xffffffffL; \
  /src/external/gpl3/binutils/dist/include/opcode/
tic6x-opcode-table.h 43 #define OP2(a, b) 2, { a, b }
134 OP2(ORXREG1, OWREG1),
139 OP2(ORREGL1, OWREGL1),
144 OP2(ORXREG1, OWREG1),
150 OP2(ORREGD1, OWREGD12),
156 OP2(ORXREG1, OWREG1),
355 OP2(OLCST, OWREG1),
361 OP2(OACST, OWREG1),
513 OP2(OLCST, ORWREG1),
518 OP2(ORXREG1, OWREG2)
    [all...]
h8300.h 546 #define MOVFROM_REG_BW(CODE, NAME, SRC, PREFIX, OP1, OP2, OP3, OP4, RELAX16) \
554 {CODE, AV_H8, 6, NAME, {{SRC, DISP32DST, E}}, {{7, 8, B30 | DSTDISPREG, 0, 6, OP2, 10, SRC, MEMRELAX | DSTDISP32LIST, E}}}, \
558 {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{7, 8, B30 | DSTDISPREG, 1, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \
559 {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{7, 8, B30 | DSTDISPREG, 2, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \
560 {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{7, 8, B30 | DSTDISPREG, 3, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \
561 {CODE, AV_H8, 4, NAME, {{SRC, ABS16DST, E}}, {{ 6, OP2, 8, SRC, RELAX16 | DSTABS16LIST, E}}}, \
562 {CODE, AV_H8, 6, NAME, {{SRC, ABS32DST, E}}, {{ 6, OP2, 10, SRC, MEMRELAX | DSTABS32LIST, E}}}
564 #define MOVTO_REG_BW(CODE, NAME, DST, PREFIX, OP1, OP2, OP3, OP4, RELAX16) \
572 {CODE, AV_H8, 6, NAME, {{DISP32SRC, DST, E}}, {{7, 8, B30 | DISPREG, 0, 6, OP2, 2, DST, MEMRELAX | DISP32LIST, E}}}, \
576 {CODE, AV_H8SX, 0, NAME, {{INDEXB32, DST, E}}, {{7, 8, B30 | DISPREG, 1, 6, OP2, 2, DST, DISP32LIST, E}}},
    [all...]
  /src/external/gpl3/binutils.old/dist/include/opcode/
tic6x-opcode-table.h 43 #define OP2(a, b) 2, { a, b }
134 OP2(ORXREG1, OWREG1),
139 OP2(ORREGL1, OWREGL1),
144 OP2(ORXREG1, OWREG1),
150 OP2(ORREGD1, OWREGD12),
156 OP2(ORXREG1, OWREG1),
355 OP2(OLCST, OWREG1),
361 OP2(OACST, OWREG1),
513 OP2(OLCST, ORWREG1),
518 OP2(ORXREG1, OWREG2)
    [all...]
h8300.h 546 #define MOVFROM_REG_BW(CODE, NAME, SRC, PREFIX, OP1, OP2, OP3, OP4, RELAX16) \
554 {CODE, AV_H8, 6, NAME, {{SRC, DISP32DST, E}}, {{7, 8, B30 | DSTDISPREG, 0, 6, OP2, 10, SRC, MEMRELAX | DSTDISP32LIST, E}}}, \
558 {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{7, 8, B30 | DSTDISPREG, 1, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \
559 {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{7, 8, B30 | DSTDISPREG, 2, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \
560 {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{7, 8, B30 | DSTDISPREG, 3, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \
561 {CODE, AV_H8, 4, NAME, {{SRC, ABS16DST, E}}, {{ 6, OP2, 8, SRC, RELAX16 | DSTABS16LIST, E}}}, \
562 {CODE, AV_H8, 6, NAME, {{SRC, ABS32DST, E}}, {{ 6, OP2, 10, SRC, MEMRELAX | DSTABS32LIST, E}}}
564 #define MOVTO_REG_BW(CODE, NAME, DST, PREFIX, OP1, OP2, OP3, OP4, RELAX16) \
572 {CODE, AV_H8, 6, NAME, {{DISP32SRC, DST, E}}, {{7, 8, B30 | DISPREG, 0, 6, OP2, 2, DST, MEMRELAX | DISP32LIST, E}}}, \
576 {CODE, AV_H8SX, 0, NAME, {{INDEXB32, DST, E}}, {{7, 8, B30 | DISPREG, 1, 6, OP2, 2, DST, DISP32LIST, E}}},
    [all...]
  /src/external/gpl3/gdb.old/dist/include/opcode/
tic6x-opcode-table.h 43 #define OP2(a, b) 2, { a, b }
134 OP2(ORXREG1, OWREG1),
139 OP2(ORREGL1, OWREGL1),
144 OP2(ORXREG1, OWREG1),
150 OP2(ORREGD1, OWREGD12),
156 OP2(ORXREG1, OWREG1),
355 OP2(OLCST, OWREG1),
361 OP2(OACST, OWREG1),
513 OP2(OLCST, ORWREG1),
518 OP2(ORXREG1, OWREG2)
    [all...]
h8300.h 546 #define MOVFROM_REG_BW(CODE, NAME, SRC, PREFIX, OP1, OP2, OP3, OP4, RELAX16) \
554 {CODE, AV_H8, 6, NAME, {{SRC, DISP32DST, E}}, {{7, 8, B30 | DSTDISPREG, 0, 6, OP2, 10, SRC, MEMRELAX | DSTDISP32LIST, E}}}, \
558 {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{7, 8, B30 | DSTDISPREG, 1, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \
559 {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{7, 8, B30 | DSTDISPREG, 2, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \
560 {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{7, 8, B30 | DSTDISPREG, 3, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \
561 {CODE, AV_H8, 4, NAME, {{SRC, ABS16DST, E}}, {{ 6, OP2, 8, SRC, RELAX16 | DSTABS16LIST, E}}}, \
562 {CODE, AV_H8, 6, NAME, {{SRC, ABS32DST, E}}, {{ 6, OP2, 10, SRC, MEMRELAX | DSTABS32LIST, E}}}
564 #define MOVTO_REG_BW(CODE, NAME, DST, PREFIX, OP1, OP2, OP3, OP4, RELAX16) \
572 {CODE, AV_H8, 6, NAME, {{DISP32SRC, DST, E}}, {{7, 8, B30 | DISPREG, 0, 6, OP2, 2, DST, MEMRELAX | DISP32LIST, E}}}, \
576 {CODE, AV_H8SX, 0, NAME, {{INDEXB32, DST, E}}, {{7, 8, B30 | DISPREG, 1, 6, OP2, 2, DST, DISP32LIST, E}}},
    [all...]
  /src/external/gpl3/gdb/dist/include/opcode/
tic6x-opcode-table.h 43 #define OP2(a, b) 2, { a, b }
134 OP2(ORXREG1, OWREG1),
139 OP2(ORREGL1, OWREGL1),
144 OP2(ORXREG1, OWREG1),
150 OP2(ORREGD1, OWREGD12),
156 OP2(ORXREG1, OWREG1),
355 OP2(OLCST, OWREG1),
361 OP2(OACST, OWREG1),
513 OP2(OLCST, ORWREG1),
518 OP2(ORXREG1, OWREG2)
    [all...]
h8300.h 546 #define MOVFROM_REG_BW(CODE, NAME, SRC, PREFIX, OP1, OP2, OP3, OP4, RELAX16) \
554 {CODE, AV_H8, 6, NAME, {{SRC, DISP32DST, E}}, {{7, 8, B30 | DSTDISPREG, 0, 6, OP2, 10, SRC, MEMRELAX | DSTDISP32LIST, E}}}, \
558 {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{7, 8, B30 | DSTDISPREG, 1, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \
559 {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{7, 8, B30 | DSTDISPREG, 2, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \
560 {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{7, 8, B30 | DSTDISPREG, 3, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \
561 {CODE, AV_H8, 4, NAME, {{SRC, ABS16DST, E}}, {{ 6, OP2, 8, SRC, RELAX16 | DSTABS16LIST, E}}}, \
562 {CODE, AV_H8, 6, NAME, {{SRC, ABS32DST, E}}, {{ 6, OP2, 10, SRC, MEMRELAX | DSTABS32LIST, E}}}
564 #define MOVTO_REG_BW(CODE, NAME, DST, PREFIX, OP1, OP2, OP3, OP4, RELAX16) \
572 {CODE, AV_H8, 6, NAME, {{DISP32SRC, DST, E}}, {{7, 8, B30 | DISPREG, 0, 6, OP2, 2, DST, MEMRELAX | DISP32LIST, E}}}, \
576 {CODE, AV_H8SX, 0, NAME, {{INDEXB32, DST, E}}, {{7, 8, B30 | DISPREG, 1, 6, OP2, 2, DST, DISP32LIST, E}}},
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
R600Defines.h 39 OP2 = (1 << 11),
  /src/external/gpl3/gcc/dist/libgcc/config/msp430/
lib2hw_mul.S 93 .macro mult16 OP1, OP2, RESULT
108 MOV.W r13, &\OP2 ; Load operand 2 which triggers MPY
112 .macro mult1632 OP1, OP2, RESLO, RESHI
129 MOV.W r13, &\OP2 ; Load operand 2 which triggers MPY
134 .macro mult32 OP1, OP2, MAC_OP1, MAC_OP2, RESLO, RESHI
150 MOV.W r14, &\OP2 ; Load operand 2 Low which triggers MPY
345 .set OP2, 0x0138
387 mult16 MPY, OP2, RESLO
391 mult1632 MPYS, OP2, RESLO, RESHI
395 mult1632 MPY, OP2, RESLO, RESH
    [all...]
  /src/external/gpl3/gcc.old/dist/libgcc/config/msp430/
lib2hw_mul.S 93 .macro mult16 OP1, OP2, RESULT
108 MOV.W r13, &\OP2 ; Load operand 2 which triggers MPY
112 .macro mult1632 OP1, OP2, RESLO, RESHI
129 MOV.W r13, &\OP2 ; Load operand 2 which triggers MPY
134 .macro mult32 OP1, OP2, MAC_OP1, MAC_OP2, RESLO, RESHI
150 MOV.W r14, &\OP2 ; Load operand 2 Low which triggers MPY
345 .set OP2, 0x0138
387 mult16 MPY, OP2, RESLO
391 mult1632 MPYS, OP2, RESLO, RESHI
395 mult1632 MPY, OP2, RESLO, RESH
    [all...]

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