| /src/external/gpl3/binutils/dist/opcodes/ |
| cr16-opc.c | 138 #define SHIFT_INST_A(NAME, OPC1, OPC2, SHIFT, OP1, OP2) \
140 {NAME, 1, OPC1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}}, \
142 {NAME, 1, OPC1+1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}},\
150 #define SHIFT_INST_L(NAME, OPC1, OPC2, SHIFT, OP1, OP2) \
152 {NAME, 1, OPC1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}}, \
294 #define CSTBIT_INST_B(NAME, OP, OPC1, OPC2, OPC3, OPC4) \
300 {NAME, 2, OPC1, 24, CSTBIT_INS, {{OP,20}, {rindex7_abs20,0}}}, \
319 #define CSTBIT_INST_W(NAME, OP, OPC1, OPC2, OPC3, OPC4) \
321 {NAME, 2, OPC1+6, 24, CSTBIT_INS, {{OP,20},{abs20,0}}}, \
331 {NAME, 1, OPC1+5, 24, CSTBIT_INS, {{OP,20}, {rpbase_disps0,16}}},
[all...] |
| crx-opc.c | 87 #define SHIFT_INST(NAME, OPRD, OPC1, SHIFT1, OPC2) \
91 {NAME, 1, OPC1, SHIFT1, SHIFT_INS, {{OPRD,20}, {regr,16}}}, \
157 #define CMPBR_INST(NAME, OPC1, OPC2, C4) \
159 {NAME, 2, ((0x300+OPC1)<<12)+C4, 8, CMPBR_INS | FMT_3| RELAXABLE, \
162 {NAME, 3, ((0x310+OPC1)<<12)+C4, 8, CMPBR_INS | FMT_3 | RELAXABLE, \
348 #define LD_REG_INST(NAME, OPC1, OPC2, DISP) \
350 {NAME, 2, 0x320+OPC1, 20, LD_STOR_INS | REVERSE_MATCH, \
353 {NAME, 3, 0x330+OPC1, 20, LD_STOR_INS | REVERSE_MATCH, \
365 {NAME, 2, 0x32C+OPC1, 20, LD_STOR_INS | REVERSE_MATCH, \
368 {NAME, 3, 0x33C+OPC1, 20, LD_STOR_INS | REVERSE_MATCH,
[all...] |
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| cr16-opc.c | 138 #define SHIFT_INST_A(NAME, OPC1, OPC2, SHIFT, OP1, OP2) \
140 {NAME, 1, OPC1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}}, \
142 {NAME, 1, OPC1+1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}},\
150 #define SHIFT_INST_L(NAME, OPC1, OPC2, SHIFT, OP1, OP2) \
152 {NAME, 1, OPC1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}}, \
294 #define CSTBIT_INST_B(NAME, OP, OPC1, OPC2, OPC3, OPC4) \
300 {NAME, 2, OPC1, 24, CSTBIT_INS, {{OP,20}, {rindex7_abs20,0}}}, \
319 #define CSTBIT_INST_W(NAME, OP, OPC1, OPC2, OPC3, OPC4) \
321 {NAME, 2, OPC1+6, 24, CSTBIT_INS, {{OP,20},{abs20,0}}}, \
331 {NAME, 1, OPC1+5, 24, CSTBIT_INS, {{OP,20}, {rpbase_disps0,16}}},
[all...] |
| crx-opc.c | 87 #define SHIFT_INST(NAME, OPRD, OPC1, SHIFT1, OPC2) \
91 {NAME, 1, OPC1, SHIFT1, SHIFT_INS, {{OPRD,20}, {regr,16}}}, \
157 #define CMPBR_INST(NAME, OPC1, OPC2, C4) \
159 {NAME, 2, ((0x300+OPC1)<<12)+C4, 8, CMPBR_INS | FMT_3| RELAXABLE, \
162 {NAME, 3, ((0x310+OPC1)<<12)+C4, 8, CMPBR_INS | FMT_3 | RELAXABLE, \
348 #define LD_REG_INST(NAME, OPC1, OPC2, DISP) \
350 {NAME, 2, 0x320+OPC1, 20, LD_STOR_INS | REVERSE_MATCH, \
353 {NAME, 3, 0x330+OPC1, 20, LD_STOR_INS | REVERSE_MATCH, \
365 {NAME, 2, 0x32C+OPC1, 20, LD_STOR_INS | REVERSE_MATCH, \
368 {NAME, 3, 0x33C+OPC1, 20, LD_STOR_INS | REVERSE_MATCH,
[all...] |
| /src/external/gpl3/gdb/dist/opcodes/ |
| cr16-opc.c | 138 #define SHIFT_INST_A(NAME, OPC1, OPC2, SHIFT, OP1, OP2) \
140 {NAME, 1, OPC1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}}, \
142 {NAME, 1, OPC1+1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}},\
150 #define SHIFT_INST_L(NAME, OPC1, OPC2, SHIFT, OP1, OP2) \
152 {NAME, 1, OPC1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}}, \
294 #define CSTBIT_INST_B(NAME, OP, OPC1, OPC2, OPC3, OPC4) \
300 {NAME, 2, OPC1, 24, CSTBIT_INS, {{OP,20}, {rindex7_abs20,0}}}, \
319 #define CSTBIT_INST_W(NAME, OP, OPC1, OPC2, OPC3, OPC4) \
321 {NAME, 2, OPC1+6, 24, CSTBIT_INS, {{OP,20},{abs20,0}}}, \
331 {NAME, 1, OPC1+5, 24, CSTBIT_INS, {{OP,20}, {rpbase_disps0,16}}},
[all...] |
| crx-opc.c | 87 #define SHIFT_INST(NAME, OPRD, OPC1, SHIFT1, OPC2) \
91 {NAME, 1, OPC1, SHIFT1, SHIFT_INS, {{OPRD,20}, {regr,16}}}, \
157 #define CMPBR_INST(NAME, OPC1, OPC2, C4) \
159 {NAME, 2, ((0x300+OPC1)<<12)+C4, 8, CMPBR_INS | FMT_3| RELAXABLE, \
162 {NAME, 3, ((0x310+OPC1)<<12)+C4, 8, CMPBR_INS | FMT_3 | RELAXABLE, \
348 #define LD_REG_INST(NAME, OPC1, OPC2, DISP) \
350 {NAME, 2, 0x320+OPC1, 20, LD_STOR_INS | REVERSE_MATCH, \
353 {NAME, 3, 0x330+OPC1, 20, LD_STOR_INS | REVERSE_MATCH, \
365 {NAME, 2, 0x32C+OPC1, 20, LD_STOR_INS | REVERSE_MATCH, \
368 {NAME, 3, 0x33C+OPC1, 20, LD_STOR_INS | REVERSE_MATCH,
[all...] |
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| cr16-opc.c | 138 #define SHIFT_INST_A(NAME, OPC1, OPC2, SHIFT, OP1, OP2) \
140 {NAME, 1, OPC1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}}, \
142 {NAME, 1, OPC1+1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}},\
150 #define SHIFT_INST_L(NAME, OPC1, OPC2, SHIFT, OP1, OP2) \
152 {NAME, 1, OPC1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}}, \
294 #define CSTBIT_INST_B(NAME, OP, OPC1, OPC2, OPC3, OPC4) \
300 {NAME, 2, OPC1, 24, CSTBIT_INS, {{OP,20}, {rindex7_abs20,0}}}, \
319 #define CSTBIT_INST_W(NAME, OP, OPC1, OPC2, OPC3, OPC4) \
321 {NAME, 2, OPC1+6, 24, CSTBIT_INS, {{OP,20},{abs20,0}}}, \
331 {NAME, 1, OPC1+5, 24, CSTBIT_INS, {{OP,20}, {rpbase_disps0,16}}},
[all...] |
| crx-opc.c | 87 #define SHIFT_INST(NAME, OPRD, OPC1, SHIFT1, OPC2) \
91 {NAME, 1, OPC1, SHIFT1, SHIFT_INS, {{OPRD,20}, {regr,16}}}, \
157 #define CMPBR_INST(NAME, OPC1, OPC2, C4) \
159 {NAME, 2, ((0x300+OPC1)<<12)+C4, 8, CMPBR_INS | FMT_3| RELAXABLE, \
162 {NAME, 3, ((0x310+OPC1)<<12)+C4, 8, CMPBR_INS | FMT_3 | RELAXABLE, \
348 #define LD_REG_INST(NAME, OPC1, OPC2, DISP) \
350 {NAME, 2, 0x320+OPC1, 20, LD_STOR_INS | REVERSE_MATCH, \
353 {NAME, 3, 0x330+OPC1, 20, LD_STOR_INS | REVERSE_MATCH, \
365 {NAME, 2, 0x32C+OPC1, 20, LD_STOR_INS | REVERSE_MATCH, \
368 {NAME, 3, 0x33C+OPC1, 20, LD_STOR_INS | REVERSE_MATCH,
[all...] |
| /src/sys/external/bsd/sljit/dist/sljit_src/ |
| sljitNativeSPARC_common.c | 119 #define OPC1(opcode) ((opcode) << 30)
124 #define ADD (OPC1(0x2) | OPC3(0x00))
125 #define ADDC (OPC1(0x2) | OPC3(0x08))
126 #define AND (OPC1(0x2) | OPC3(0x01))
127 #define ANDN (OPC1(0x2) | OPC3(0x05))
128 #define CALL (OPC1(0x1))
129 #define FABSS (OPC1(0x2) | OPC3(0x34) | DOP(0x09))
130 #define FADDD (OPC1(0x2) | OPC3(0x34) | DOP(0x42))
131 #define FADDS (OPC1(0x2) | OPC3(0x34) | DOP(0x41))
132 #define FCMPD (OPC1(0x2) | OPC3(0x35) | DOP(0x52)
[all...] |
