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      1 //===-- ARMMCTargetDesc.h - ARM Target Descriptions -------------*- C++ -*-===//
      2 //
      3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
      4 // See https://llvm.org/LICENSE.txt for license information.
      5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
      6 //
      7 //===----------------------------------------------------------------------===//
      8 //
      9 // This file provides ARM specific target descriptions.
     10 //
     11 //===----------------------------------------------------------------------===//
     12 
     13 #ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCTARGETDESC_H
     14 #define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCTARGETDESC_H
     15 
     16 #include "llvm/Support/DataTypes.h"
     17 #include "llvm/MC/MCInstrDesc.h"
     18 #include <memory>
     19 #include <string>
     20 
     21 namespace llvm {
     22 class formatted_raw_ostream;
     23 class MCAsmBackend;
     24 class MCCodeEmitter;
     25 class MCContext;
     26 class MCInstrInfo;
     27 class MCInstPrinter;
     28 class MCObjectTargetWriter;
     29 class MCObjectWriter;
     30 class MCRegisterInfo;
     31 class MCSubtargetInfo;
     32 class MCStreamer;
     33 class MCTargetOptions;
     34 class MCRelocationInfo;
     35 class MCTargetStreamer;
     36 class StringRef;
     37 class Target;
     38 class Triple;
     39 class raw_ostream;
     40 class raw_pwrite_stream;
     41 
     42 namespace ARM_MC {
     43 std::string ParseARMTriple(const Triple &TT, StringRef CPU);
     44 void initLLVMToCVRegMapping(MCRegisterInfo *MRI);
     45 
     46 bool isPredicated(const MCInst &MI, const MCInstrInfo *MCII);
     47 bool isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII);
     48 
     49 template<class Inst>
     50 bool isLDMBaseRegInList(const Inst &MI) {
     51   auto BaseReg = MI.getOperand(0).getReg();
     52   for (unsigned I = 1, E = MI.getNumOperands(); I < E; ++I) {
     53     const auto &Op = MI.getOperand(I);
     54     if (Op.isReg() && Op.getReg() == BaseReg)
     55       return true;
     56   }
     57   return false;
     58 }
     59 
     60 /// Create a ARM MCSubtargetInfo instance. This is exposed so Asm parser, etc.
     61 /// do not need to go through TargetRegistry.
     62 MCSubtargetInfo *createARMMCSubtargetInfo(const Triple &TT, StringRef CPU,
     63                                           StringRef FS);
     64 }
     65 
     66 MCTargetStreamer *createARMNullTargetStreamer(MCStreamer &S);
     67 MCTargetStreamer *createARMTargetAsmStreamer(MCStreamer &S,
     68                                              formatted_raw_ostream &OS,
     69                                              MCInstPrinter *InstPrint,
     70                                              bool isVerboseAsm);
     71 MCTargetStreamer *createARMObjectTargetStreamer(MCStreamer &S,
     72                                                 const MCSubtargetInfo &STI);
     73 
     74 MCCodeEmitter *createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
     75                                         const MCRegisterInfo &MRI,
     76                                         MCContext &Ctx);
     77 
     78 MCCodeEmitter *createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
     79                                         const MCRegisterInfo &MRI,
     80                                         MCContext &Ctx);
     81 
     82 MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCSubtargetInfo &STI,
     83                                     const MCRegisterInfo &MRI,
     84                                     const MCTargetOptions &Options);
     85 
     86 MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCSubtargetInfo &STI,
     87                                     const MCRegisterInfo &MRI,
     88                                     const MCTargetOptions &Options);
     89 
     90 // Construct a PE/COFF machine code streamer which will generate a PE/COFF
     91 // object file.
     92 MCStreamer *createARMWinCOFFStreamer(MCContext &Context,
     93                                      std::unique_ptr<MCAsmBackend> &&MAB,
     94                                      std::unique_ptr<MCObjectWriter> &&OW,
     95                                      std::unique_ptr<MCCodeEmitter> &&Emitter,
     96                                      bool RelaxAll,
     97                                      bool IncrementalLinkerCompatible);
     98 
     99 /// Construct an ELF Mach-O object writer.
    100 std::unique_ptr<MCObjectTargetWriter> createARMELFObjectWriter(uint8_t OSABI);
    101 
    102 /// Construct an ARM Mach-O object writer.
    103 std::unique_ptr<MCObjectTargetWriter>
    104 createARMMachObjectWriter(bool Is64Bit, uint32_t CPUType,
    105                           uint32_t CPUSubtype);
    106 
    107 /// Construct an ARM PE/COFF object writer.
    108 std::unique_ptr<MCObjectTargetWriter>
    109 createARMWinCOFFObjectWriter();
    110 
    111 /// Construct ARM Mach-O relocation info.
    112 MCRelocationInfo *createARMMachORelocationInfo(MCContext &Ctx);
    113 
    114 namespace ARM {
    115 enum OperandType {
    116   OPERAND_VPRED_R = MCOI::OPERAND_FIRST_TARGET,
    117   OPERAND_VPRED_N,
    118 };
    119 inline bool isVpred(OperandType op) {
    120   return op == OPERAND_VPRED_R || op == OPERAND_VPRED_N;
    121 }
    122 inline bool isVpred(uint8_t op) {
    123   return isVpred(static_cast<OperandType>(op));
    124 }
    125 
    126 bool isCDECoproc(size_t Coproc, const MCSubtargetInfo &STI);
    127 
    128 } // end namespace ARM
    129 
    130 } // End llvm namespace
    131 
    132 // Defines symbolic names for ARM registers.  This defines a mapping from
    133 // register name to register number.
    134 //
    135 #define GET_REGINFO_ENUM
    136 #include "ARMGenRegisterInfo.inc"
    137 
    138 // Defines symbolic names for the ARM instructions.
    139 //
    140 #define GET_INSTRINFO_ENUM
    141 #include "ARMGenInstrInfo.inc"
    142 
    143 #define GET_SUBTARGETINFO_ENUM
    144 #include "ARMGenSubtargetInfo.inc"
    145 
    146 #endif
    147