| /src/sys/external/isc/atheros_hal/dist/ar5210/ |
| ar5210_power.c | 36 OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE, AR_SCR_SLE_ALLOW);
56 OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE, AR_SCR_SLE_WAKE);
64 OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE,
90 OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE, AR_SCR_SLE_SLP);
|
| ar5210_misc.c | 430 OS_REG_RMW_FIELD(ah, AR_IFS0, AR_IFS0_SIFS,
481 OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
528 OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
|
| /src/sys/external/isc/atheros_hal/dist/ar5211/ |
| ar5211_power.c | 45 OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE, AR_SCR_SLE_WAKE);
53 OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE,
79 OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE, AR_SCR_SLE_SLP);
92 OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE, AR_SCR_SLE_NORM);
|
| ar5211_beacon.c | 172 OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLDUR,
|
| ar5211_misc.c | 484 OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
531 OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
|
| ar5211_xmit.c | 190 OS_REG_RMW_FIELD(ah, AR_IMR_S2,
|
| ar5211_reset.c | 432 OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
1237 OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
|
| /src/sys/external/isc/atheros_hal/dist/ar5416/ |
| ar5416_gpio.c | 172 OS_REG_RMW_FIELD(ah, AR_INTR_ASYNC_ENABLE,
177 OS_REG_RMW_FIELD(ah, AR_INTR_ASYNC_MASK,
183 OS_REG_RMW_FIELD(ah, AR_INTR_SYNC_ENABLE,
188 OS_REG_RMW_FIELD(ah, AR_INTR_SYNC_MASK,
193 OS_REG_RMW_FIELD(ah, AR_INTR_SYNC_CAUSE,
205 OS_REG_RMW_FIELD(ah, AR_GPIO_INTR_POL,
211 OS_REG_RMW_FIELD(ah, AR_INTR_ASYNC_ENABLE,
216 OS_REG_RMW_FIELD(ah, AR_INTR_ASYNC_MASK,
222 OS_REG_RMW_FIELD(ah, AR_INTR_SYNC_ENABLE,
227 OS_REG_RMW_FIELD(ah, AR_INTR_SYNC_MASK
[all...] |
| ar5416_cal_iq.c | 122 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4_CHAIN(i),
124 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4_CHAIN(i),
|
| ar5416_ani.c | 228 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
230 OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
232 OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
234 OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
253 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
255 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
257 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
259 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
261 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
263 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW
[all...] |
| ar9285_reset.c | 268 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
273 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
275 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_XATTEN1_DB,
277 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
279 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_XATTEN2_DB,
283 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
285 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
287 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
289 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
293 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN
[all...] |
| ar5416_reset.c | 230 OS_REG_RMW_FIELD(ah, AR_D_FPCTL, ... );
336 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
337 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
753 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3,
755 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3,
767 OS_REG_RMW_FIELD(ah, AR_PHY_HALFGI,
769 OS_REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1313 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, pModal->switchSettling);
1314 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, pModal->adcDesiredSize);
1315 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_PGA, pModal->pgaDesiredSize)
[all...] |
| ar5416_beacon.c | 166 OS_REG_RMW_FIELD(ah, AR_RSSI_THR,
|
| ar9280.c | 121 OS_REG_RMW_FIELD(ah, AR_AN_SYNTH9,
|
| ar5416_cal.c | 68 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,
|
| /src/sys/external/isc/atheros_hal/dist/ar5312/ |
| ar5312_misc.c | 114 OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32, 1);
119 OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32,
147 OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32,
|
| ar5312_reset.c | 290 OS_REG_RMW_FIELD(ah, AR_PHY_DAG_CTRLCCK,
304 OS_REG_RMW_FIELD(ah, AR_D_FPCTL, ... );
319 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN, AR_PHY_RXGAIN_TXRX_RF_MAX, 0x0F);
323 OS_REG_RMW_FIELD(ah, AR_PHY_CCK_RXCTRL4, AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT, 12);
330 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_AGC, 32);
416 OS_REG_RMW_FIELD(ah, AR_PHY_TX_CTL,
492 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,
|
| /src/sys/external/isc/atheros_hal/dist/ar5212/ |
| ar5212_power.c | 51 * which when blindly written back with OS_REG_RMW_FIELD
99 OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE, AR_SCR_SLE_SLP);
112 OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE, AR_SCR_SLE_NORM);
|
| ar5212_ani.c | 277 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
279 OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
281 OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
283 OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
302 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
304 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
306 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
308 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
310 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
312 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW
[all...] |
| ar5212_misc.c | 505 OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
552 OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
674 OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32, 1);
676 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_SEL, 1);
684 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0x2);
690 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0x3);
693 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0x0);
694 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_SEL, 0);
711 OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32,
724 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0)
[all...] |
| ar5212_reset.c | 307 OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
344 OS_REG_RMW_FIELD(ah, AR_PHY_DAG_CTRLCCK,
358 OS_REG_RMW_FIELD(ah, AR_D_FPCTL, ... );
459 OS_REG_RMW_FIELD(ah, AR_PHY_TX_CTL,
529 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,
1068 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,
1070 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,
1086 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,
1499 OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
1541 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING,
[all...] |
| ar2316.c | 552 OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
|
| ar2317.c | 530 OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
|
| ar2413.c | 546 OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
|
| /src/sys/external/isc/atheros_hal/dist/ |
| ah_internal.h | 509 #define OS_REG_RMW_FIELD(_a, _r, _f, _v) \
|
