| /src/sys/external/isc/atheros_hal/dist/ar5312/ |
| ar5312_misc.c | 46 OS_REG_WRITE(ah, resOffset+AR5312_PCICFG,
106 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);
107 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x0d);
108 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0c);
109 OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x03);
110 OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0x05);
111 OS_REG_WRITE(ah, AR_PHY_REFCLKPD,
115 OS_REG_WRITE(ah, AR_TSF_PARM, 61); /* 32 KHz TSF incr */
118 OS_REG_WRITE(ah, AR_TSF_PARM, 1); /* 32 MHz TSF incr */
122 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f)
[all...] |
| ar5312_reset.c | 65 OS_REG_WRITE(ah, reg, V(i, 1));
250 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
266 OS_REG_WRITE(ah, AR_PHY_ADC_CTL,
280 OS_REG_WRITE(ah, AR_PHY_TXPWRADJ,
284 OS_REG_WRITE(ah, AR_PHY_TXPWRADJ, 0);
294 OS_REG_WRITE(ah, AR_SEQ_MASK, 0x0000000F);
299 OS_REG_WRITE(ah, AR_PHY_BLUETOOTH, 0);
312 OS_REG_WRITE(ah, AR_PHY_SIGMA_DELTA,
326 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x04);
333 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e)
[all...] |
| ar5315_gpio.c | 44 OS_REG_WRITE(ah, gpioOffset+AR5315_GPIODIR,
61 OS_REG_WRITE(ah, gpioOffset+AR5315_GPIODIR,
83 OS_REG_WRITE(ah, gpioOffset+AR5315_GPIODO, reg);
123 OS_REG_WRITE(ah, gpioOffset+AR5315_GPIOINT, val);
|
| ar5312_gpio.c | 44 OS_REG_WRITE(ah, gpioOffset+AR5312_GPIOCR,
61 OS_REG_WRITE(ah, gpioOffset+AR5312_GPIOCR,
83 OS_REG_WRITE(ah, gpioOffset+AR5312_GPIODO, reg);
124 OS_REG_WRITE(ah, gpioOffset+AR5312_GPIOCR, val);
|
| /src/sys/external/isc/atheros_hal/dist/ar5210/ |
| ar5210_beacon.c | 36 OS_REG_WRITE(ah, AR_TIMER0, bt->bt_nexttbtt);
37 OS_REG_WRITE(ah, AR_TIMER1, bt->bt_nextdba);
38 OS_REG_WRITE(ah, AR_TIMER2, bt->bt_nextswba);
39 OS_REG_WRITE(ah, AR_TIMER3, bt->bt_nextatim);
43 OS_REG_WRITE(ah, AR_BEACON, bt->bt_intval);
87 OS_REG_WRITE(ah, AR_TIMER0, 0); /* no beacons */
91 OS_REG_WRITE(ah, AR_STA_ID1,
93 OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_PERIOD);
115 OS_REG_WRITE(ah, AR_STA_ID1,
120 OS_REG_WRITE(ah, AR_CFP_PERIOD, bs->bs_cfpperiod)
[all...] |
| ar5210_keycache.c | 60 OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
61 OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
62 OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
63 OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
64 OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
65 OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), 0);
66 OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
67 OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
97 OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
98 OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(entry)
[all...] |
| ar5210_reset.c | 124 OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr));
125 OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4));
130 OS_REG_WRITE(ah, AR_BCR, INIT_BCON_CNTRL_REG);
131 OS_REG_WRITE(ah, AR_PCICFG,
135 OS_REG_WRITE(ah, AR_BCR, INIT_BCON_CNTRL_REG | AR_BCR_BCMD);
136 OS_REG_WRITE(ah, AR_PCICFG,
140 OS_REG_WRITE(ah, AR_BCR, INIT_BCON_CNTRL_REG);
141 OS_REG_WRITE(ah, AR_PCICFG,
145 OS_REG_WRITE(ah, AR_BCR, INIT_BCON_CNTRL_REG);
146 OS_REG_WRITE(ah, AR_PCICFG
[all...] |
| ar5210_recv.c | 44 OS_REG_WRITE(ah, AR_RXDP, rxdp);
54 OS_REG_WRITE(ah, AR_CR, AR_CR_RXE);
65 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */
85 OS_REG_WRITE(ah, AR_DIAG_SW,
95 OS_REG_WRITE(ah, AR_DIAG_SW,
106 OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0);
107 OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1);
122 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val &~ (1<<(ix-32))));
125 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val &~ (1<<ix)));
142 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val | (1<<(ix-32))))
[all...] |
| ar5210_xmit.c | 181 OS_REG_WRITE(ah, AR_SLOT_TIME, INIT_SLOT_TIME_TURBO);
182 OS_REG_WRITE(ah, AR_TIME_OUT, INIT_ACK_CTS_TIMEOUT_TURBO);
183 OS_REG_WRITE(ah, AR_USEC, INIT_TRANSMIT_LATENCY_TURBO);
184 OS_REG_WRITE(ah, AR_IFS0,
188 OS_REG_WRITE(ah, AR_IFS1, INIT_PROTO_TIME_CNTRL_TURBO);
189 OS_REG_WRITE(ah, AR_PHY(17),
191 OS_REG_WRITE(ah, AR_PHY_FRCTL,
198 OS_REG_WRITE(ah, AR_SLOT_TIME, INIT_SLOT_TIME);
199 OS_REG_WRITE(ah, AR_TIME_OUT, INIT_ACK_CTS_TIMEOUT);
200 OS_REG_WRITE(ah, AR_USEC, INIT_TRANSMIT_LATENCY)
[all...] |
| ar5210_interrupts.c | 105 OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
124 OS_REG_WRITE(ah, AR_IMR, mask);
130 OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
|
| /src/sys/external/isc/atheros_hal/dist/ar5211/ |
| ar5211_beacon.c | 39 OS_REG_WRITE(ah, AR_TIMER0, bt->bt_nexttbtt);
40 OS_REG_WRITE(ah, AR_TIMER1, bt->bt_nextdba);
41 OS_REG_WRITE(ah, AR_TIMER2, bt->bt_nextswba);
42 OS_REG_WRITE(ah, AR_TIMER3, bt->bt_nextatim);
46 OS_REG_WRITE(ah, AR_BEACON, bt->bt_intval);
98 OS_REG_WRITE(ah, AR_TIMER0, 0); /* no beacons */
102 OS_REG_WRITE(ah, AR_STA_ID1,
104 OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_PERIOD);
123 OS_REG_WRITE(ah, AR_STA_ID1,
127 OS_REG_WRITE(ah, AR_CFP_PERIOD, bs->bs_cfpperiod)
[all...] |
| ar5211_keycache.c | 64 OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
65 OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
66 OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
67 OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
68 OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
69 OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), 0);
70 OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
71 OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
106 OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
107 OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID)
[all...] |
| ar5211_recv.c | 44 OS_REG_WRITE(ah, AR_RXDP, rxdp);
55 OS_REG_WRITE(ah, AR_CR, AR_CR_RXE);
64 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */
86 OS_REG_WRITE(ah, AR_DIAG_SW,
96 OS_REG_WRITE(ah, AR_DIAG_SW,
107 OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0);
108 OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1);
123 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val &~ (1<<(ix-32))));
126 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val &~ (1<<ix)));
143 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val | (1<<(ix-32))))
[all...] |
| ar5211_reset.c | 293 OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000007);
295 OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000047);
323 OS_REG_WRITE(ah, ar5211Mode2_4[i][0],
332 OS_REG_WRITE(ah, ar5211Modes[i][0], ar5211Modes[i][modesIndex]);
336 OS_REG_WRITE(ah, ar5211BB_RfGain[i][0], ar5211BB_RfGain[i][freqIndex]);
343 OS_REG_WRITE(ah, reg, ar5211Common[i][1]);
357 OS_REG_WRITE(ah, AR_USEC,
361 OS_REG_WRITE(ah, AR5311_QDCLKGATE, 0);
364 OS_REG_WRITE(ah, 0x00009878, 0x00000008);
367 OS_REG_WRITE(ah, AR_DIAG_SW
[all...] |
| ar5211_xmit.c | 67 OS_REG_WRITE(ah, AR_TXCFG, (txcfg &~ AR_TXCFG_FTRIG_M) |
182 OS_REG_WRITE(ah, AR_IMR_S0,
186 OS_REG_WRITE(ah, AR_IMR_S1,
268 OS_REG_WRITE(ah, AR_DLCL_IFS(q),
274 OS_REG_WRITE(ah, AR_DRETRY_LIMIT(q),
282 OS_REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);
286 OS_REG_WRITE(ah, AR_DMISC(q), AR5311_D_MISC_SEQ_NUM_CONTROL);
290 OS_REG_WRITE(ah, AR_QCBRCFG(q),
293 OS_REG_WRITE(ah, AR_QMISC(q),
300 OS_REG_WRITE(ah, AR_QRDYTIMECFG(q)
[all...] |
| /src/sys/external/isc/atheros_hal/dist/ar5212/ |
| ar5212_keycache.c | 78 OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
79 OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
80 OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
81 OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
82 OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
83 OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
84 OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
85 OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
90 OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
91 OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0)
[all...] |
| ar5212_beacon.c | 37 OS_REG_WRITE(ah, AR_TIMER0, bt->bt_nexttbtt);
38 OS_REG_WRITE(ah, AR_TIMER1, bt->bt_nextdba);
39 OS_REG_WRITE(ah, AR_TIMER2, bt->bt_nextswba);
40 OS_REG_WRITE(ah, AR_TIMER3, bt->bt_nextatim);
54 OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_RESET_TSF);
56 OS_REG_WRITE(ah, AR_BEACON, bt->bt_intval);
109 OS_REG_WRITE(ah, AR_TIMER0, 0); /* no beacons */
113 OS_REG_WRITE(ah, AR_STA_ID1,
115 OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_PERIOD);
133 OS_REG_WRITE(ah, AR_STA_ID1
[all...] |
| ar5212_eeprom.c | 38 OS_REG_WRITE(ah, AR_EEPROM_ADDR, off);
39 OS_REG_WRITE(ah, AR_EEPROM_CMD, AR_EEPROM_CMD_READ);
|
| ar5212_recv.c | 43 OS_REG_WRITE(ah, AR_RXDP, rxdp);
53 OS_REG_WRITE(ah, AR_CR, AR_CR_RXE);
62 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */
85 OS_REG_WRITE(ah, AR_DIAG_SW,
98 OS_REG_WRITE(ah, AR_DIAG_SW,
110 OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0);
111 OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1);
126 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val &~ (1<<(ix-32))));
129 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val &~ (1<<ix)));
146 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val | (1<<(ix-32))))
[all...] |
| ar5212_misc.c | 72 OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssidmask));
73 OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4));
211 OS_REG_WRITE(ah, AR_PCICFG, bits);
227 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
228 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid+4) |
278 OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF);
286 OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF);
317 OS_REG_WRITE(ah, AR_STA_ID1, reg | AR_STA_ID1_BASE_RATE_11B);
319 OS_REG_WRITE(ah, AR_STA_ID1, reg &~ AR_STA_ID1_BASE_RATE_11B);
363 OS_REG_WRITE(ah, AR_MIBC
[all...] |
| ar5212_gpio.c | 47 OS_REG_WRITE(ah, AR_GPIOCR,
61 OS_REG_WRITE(ah, AR_GPIOCR,
82 OS_REG_WRITE(ah, AR_GPIODO, reg);
120 OS_REG_WRITE(ah, AR_GPIOCR, val);
|
| ar5212_reset.c | 79 OS_REG_WRITE(ah, reg, V(r, 1));
291 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
315 OS_REG_WRITE(ah, AR_PHY_ADC_CTL,
332 OS_REG_WRITE(ah, AR_PHY_TXPWRADJ,
338 OS_REG_WRITE(ah, AR_PHY_TXPWRADJ, 0);
348 OS_REG_WRITE(ah, AR_SEQ_MASK, 0x0000000F);
353 OS_REG_WRITE(ah, AR_PHY_BLUETOOTH, 0);
365 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e);
373 OS_REG_WRITE(ah, AR_PHY_FAST_ADC, newReg);
407 OS_REG_WRITE(ah, AR_D_SEQNUM, saveFrameSeqCount)
[all...] |
| /src/sys/external/isc/atheros_hal/dist/ar5416/ |
| ar5416_beacon.c | 40 OS_REG_WRITE(ah, AR_NEXT_TBTT, TU_TO_USEC(bt->bt_nexttbtt));
41 OS_REG_WRITE(ah, AR_NEXT_DBA, TU_TO_USEC(bt->bt_nextdba) >> 3);
42 OS_REG_WRITE(ah, AR_NEXT_SWBA, TU_TO_USEC(bt->bt_nextswba) >> 3);
43 OS_REG_WRITE(ah, AR_NEXT_NDP, TU_TO_USEC(bt->bt_nextatim));
46 OS_REG_WRITE(ah, AR5416_BEACON_PERIOD, bperiod);
47 OS_REG_WRITE(ah, AR_DBA_PERIOD, bperiod);
48 OS_REG_WRITE(ah, AR_SWBA_PERIOD, bperiod);
49 OS_REG_WRITE(ah, AR_NDP_PERIOD, bperiod);
123 OS_REG_WRITE(ah, AR_NEXT_TBTT, 0); /* no beacons */
127 OS_REG_WRITE(ah, AR_STA_ID1
[all...] |
| ar5416_interrupts.c | 147 OS_REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
148 OS_REG_WRITE(ah, AR_RC, 0);
162 OS_REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
185 OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
188 OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
191 OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
241 OS_REG_WRITE(ah, AR_IMR, mask);
250 OS_REG_WRITE(ah, AR_IMR_S2, mask | mask2);
257 OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
259 OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ)
[all...] |
| ar9280_attach.c | 186 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
279 OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode);
302 OS_REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
330 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
331 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
451 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), newVal);
458 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
493 OS_REG_WRITE(ah, AR_PHY_TIMING11, newVal);
497 OS_REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
525 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask)
[all...] |
