HomeSort by: relevance | last modified time | path
    Searched refs:OTG_H_TIMING_CNTL (Results 1 - 3 of 3) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_optc.c 230 REG_WRITE(OTG_H_TIMING_CNTL, 0);
233 REG_UPDATE(OTG_H_TIMING_CNTL,
285 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_BY2, 1);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
dcn10_optc.h 48 SRI(OTG_H_TIMING_CNTL, OTG, inst),\
120 uint32_t OTG_H_TIMING_CNTL;
amdgpu_dcn10_optc.c 296 REG_UPDATE(OTG_H_TIMING_CNTL,

Completed in 14 milliseconds