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    Searched refs:OTG_STEREO_CONTROL (Results 1 - 2 of 2) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_optc.c 99 REG_SET(OTG_STEREO_CONTROL, 0,
1200 REG_UPDATE_3(OTG_STEREO_CONTROL,
1206 REG_UPDATE(OTG_STEREO_CONTROL,
1211 REG_UPDATE(OTG_STEREO_CONTROL,
dcn10_optc.h 55 SRI(OTG_STEREO_CONTROL, OTG, inst),\
127 uint32_t OTG_STEREO_CONTROL;

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