| /src/sys/external/bsd/drm2/dist/drm/nouveau/ |
| nouveau_nvc0_fbcon.c | 49 OUT_RING (chan, 1);
54 OUT_RING (chan, ((uint32_t *)info->pseudo_palette)[rect->color]);
56 OUT_RING (chan, rect->color);
58 OUT_RING (chan, rect->dx);
59 OUT_RING (chan, rect->dy);
60 OUT_RING (chan, rect->dx + rect->width);
61 OUT_RING (chan, rect->dy + rect->height);
64 OUT_RING (chan, 3);
83 OUT_RING (chan, 0);
85 OUT_RING (chan, region->dx)
[all...] |
| nouveau_nv50_fbcon.c | 49 OUT_RING(chan, 1);
54 OUT_RING(chan, ((uint32_t *)info->pseudo_palette)[rect->color]);
56 OUT_RING(chan, rect->color);
58 OUT_RING(chan, rect->dx);
59 OUT_RING(chan, rect->dy);
60 OUT_RING(chan, rect->dx + rect->width);
61 OUT_RING(chan, rect->dy + rect->height);
64 OUT_RING(chan, 3);
83 OUT_RING(chan, 0);
85 OUT_RING(chan, region->dx)
[all...] |
| nouveau_nv04_fbcon.c | 47 OUT_RING(chan, (region->sy << 16) | region->sx);
48 OUT_RING(chan, (region->dy << 16) | region->dx);
49 OUT_RING(chan, (region->height << 16) | region->width);
67 OUT_RING(chan, (rect->rop != ROP_COPY) ? 1 : 3);
71 OUT_RING(chan, ((uint32_t *)info->pseudo_palette)[rect->color]);
73 OUT_RING(chan, rect->color);
75 OUT_RING(chan, (rect->dx << 16) | rect->dy);
76 OUT_RING(chan, (rect->width << 16) | rect->height);
110 OUT_RING(chan, (image->dy << 16) | (image->dx & 0xffff));
111 OUT_RING(chan, ((image->dy + image->height) << 16)
[all...] |
| nouveau_nvc0_fence.c | 42 OUT_RING (chan, upper_32_bits(virtual));
43 OUT_RING (chan, lower_32_bits(virtual));
44 OUT_RING (chan, sequence);
45 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
46 OUT_RING (chan, 0x00000000);
58 OUT_RING (chan, upper_32_bits(virtual));
59 OUT_RING (chan, lower_32_bits(virtual));
60 OUT_RING (chan, sequence);
61 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL |
|
| nouveau_bo.c | 833 OUT_RING (chan, handle & 0x0000ffff);
847 OUT_RING (chan, upper_32_bits(mem->vma[0].addr));
848 OUT_RING (chan, lower_32_bits(mem->vma[0].addr));
849 OUT_RING (chan, upper_32_bits(mem->vma[1].addr));
850 OUT_RING (chan, lower_32_bits(mem->vma[1].addr));
851 OUT_RING (chan, PAGE_SIZE);
852 OUT_RING (chan, PAGE_SIZE);
853 OUT_RING (chan, PAGE_SIZE);
854 OUT_RING (chan, new_reg->num_pages);
866 OUT_RING (chan, handle)
[all...] |
| nouveau_nv17_fence.c | 59 OUT_RING (prev, fctx->sema.handle);
60 OUT_RING (prev, 0);
61 OUT_RING (prev, value + 0);
62 OUT_RING (prev, value + 1);
68 OUT_RING (chan, fctx->sema.handle);
69 OUT_RING (chan, 0);
70 OUT_RING (chan, value + 1);
71 OUT_RING (chan, value + 2);
|
| nouveau_nv84_fence.c | 45 OUT_RING (chan, chan->vram.handle);
47 OUT_RING (chan, upper_32_bits(virtual));
48 OUT_RING (chan, lower_32_bits(virtual));
49 OUT_RING (chan, sequence);
50 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
51 OUT_RING (chan, 0x00000000);
63 OUT_RING (chan, chan->vram.handle);
65 OUT_RING (chan, upper_32_bits(virtual));
66 OUT_RING (chan, lower_32_bits(virtual));
67 OUT_RING (chan, sequence)
[all...] |
| nouveau_dma.h | 102 OUT_RING(struct nouveau_channel *chan, int data)
113 OUT_RING(chan, 0x00000000 | (subc << 13) | (size << 18) | mthd);
119 OUT_RING(chan, 0x40000000 | (subc << 13) | (size << 18) | mthd);
125 OUT_RING(chan, 0x20000000 | (size << 16) | (subc << 13) | (mthd >> 2));
131 OUT_RING(chan, 0x60000000 | (size << 16) | (subc << 13) | (mthd >> 2));
137 OUT_RING(chan, 0x80000000 | (data << 16) | (subc << 13) | (mthd >> 2));
|
| nouveau_dmem.c | 465 OUT_RING (chan, upper_32_bits(src_addr));
466 OUT_RING (chan, lower_32_bits(src_addr));
467 OUT_RING (chan, upper_32_bits(dst_addr));
468 OUT_RING (chan, lower_32_bits(dst_addr));
469 OUT_RING (chan, PAGE_SIZE);
470 OUT_RING (chan, PAGE_SIZE);
471 OUT_RING (chan, PAGE_SIZE);
472 OUT_RING (chan, npages);
474 OUT_RING (chan, launch_dma);
|
| nouveau_nv04_fence.c | 51 OUT_RING (chan, fence->base.seqno);
|
| nouveau_nv10_fence.c | 41 OUT_RING (chan, fence->base.seqno);
|
| nouveau_gem.c | 823 OUT_RING(chan, (nvbo->bo.offset + push[i].offset) | 2);
824 OUT_RING(chan, 0);
857 OUT_RING(chan, 0x20000000 |
859 OUT_RING(chan, 0);
861 OUT_RING(chan, 0);
|
| /src/sys/external/bsd/drm/dist/shared-core/ |
| r128_state.c | 50 OUT_RING(CCE_PACKET0(R128_AUX1_SC_LEFT, 3));
51 OUT_RING(boxes[0].x1);
52 OUT_RING(boxes[0].x2 - 1);
53 OUT_RING(boxes[0].y1);
54 OUT_RING(boxes[0].y2 - 1);
59 OUT_RING(CCE_PACKET0(R128_AUX2_SC_LEFT, 3));
60 OUT_RING(boxes[1].x1);
61 OUT_RING(boxes[1].x2 - 1);
62 OUT_RING(boxes[1].y1);
63 OUT_RING(boxes[1].y2 - 1)
[all...] |
| r600_blit.c | 1220 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
1221 OUT_RING((R600_CB_COLOR0_BASE - R600_SET_CONTEXT_REG_OFFSET) >> 2);
1222 OUT_RING(gpu_addr >> 8);
1223 OUT_RING(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));
1224 OUT_RING(2 << 0);
1227 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
1228 OUT_RING((R600_CB_COLOR0_BASE - R600_SET_CONTEXT_REG_OFFSET) >> 2);
1229 OUT_RING(gpu_addr >> 8);
1232 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
1233 OUT_RING((R600_CB_COLOR0_SIZE - R600_SET_CONTEXT_REG_OFFSET) >> 2)
[all...] |
| radeon_state.c | 438 OUT_RING(CP_PACKET0(RADEON_RE_TOP_LEFT, 0));
439 OUT_RING((box->y1 << 16) | box->x1);
440 OUT_RING(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0));
441 OUT_RING(((box->y2 - 1) << 16) | (box->x2 - 1));
470 OUT_RING(CP_PACKET0(RADEON_PP_MISC, 6));
471 OUT_RING(ctx->pp_misc);
472 OUT_RING(ctx->pp_fog_color);
473 OUT_RING(ctx->re_solid_color);
474 OUT_RING(ctx->rb3d_blendcntl);
475 OUT_RING(ctx->rb3d_depthoffset)
[all...] |
| r300_cmdbuf.c | 71 OUT_RING(CP_PACKET0(R300_RE_CLIPRECT_TL_0, nr * 2 - 1));
103 OUT_RING((box.x1 << R300_CLIPRECT_X_SHIFT) |
105 OUT_RING((box.x2 << R300_CLIPRECT_X_SHIFT) |
117 OUT_RING(CP_PACKET0(R300_RE_SCISSORS_TL, 1));
118 OUT_RING(0);
119 OUT_RING(R300_SCISSORS_X_MASK | R300_SCISSORS_Y_MASK);
144 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
145 OUT_RING(R300_RB3D_DC_FLUSH);
148 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
149 OUT_RING(RADEON_WAIT_3D_IDLECLEAN)
[all...] |
| i915_dma.c | 372 OUT_RING(cmd);
379 OUT_RING(cmd);
384 OUT_RING(0);
411 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
412 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
413 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
414 OUT_RING(DR4);
418 OUT_RING(GFX_OP_DRAWRECT_INFO);
419 OUT_RING(DR1);
420 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16))
[all...] |
| radeon_drv.h | 1945 OUT_RING( CP_PACKET0( R600_WAIT_UNTIL, 0 ) ); \
1947 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1948 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1954 OUT_RING( CP_PACKET0( R600_WAIT_UNTIL, 0 ) ); \
1956 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1957 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
1963 OUT_RING( CP_PACKET0( R600_WAIT_UNTIL, 0 ) ); \
1965 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1966 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1973 OUT_RING( CP_PACKET0( R600_WAIT_UNTIL, 0 ) );
[all...] |
| mach64_dma.c | 683 #define OUT_RING( x ) \
686 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
726 OUT_RING( MACH64_APERTURE_OFFSET + MACH64_BM_ADDR );
727 OUT_RING( page );
728 OUT_RING( MACH64_DMA_CHUNKSIZE | MACH64_DMA_HOLD_OFFSET );
729 OUT_RING( 0 );
741 OUT_RING( MACH64_APERTURE_OFFSET + MACH64_BM_ADDR );
742 OUT_RING( page );
743 OUT_RING( remainder | MACH64_DMA_HOLD_OFFSET | MACH64_DMA_EOL );
744 OUT_RING( 0 )
[all...] |
| i915_irq.c | 263 OUT_RING(MI_STORE_DWORD_INDEX);
264 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
265 OUT_RING(dev_priv->counter);
266 OUT_RING(MI_USER_INTERRUPT);
|
| r600_cp.c | 2193 OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
2194 OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT);
2196 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
2197 OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2);
2198 OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN);
2215 OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE, 5));
2216 OUT_RING(0x00000001);
2218 OUT_RING(0x00000000);
2220 OUT_RING((dev_priv->r600_max_hw_contexts - 1));
2222 OUT_RING(0x00000000)
[all...] |
| r128_drv.h | 454 OUT_RING( CCE_PACKET0( R128_WAIT_UNTIL, 0 ) ); \
455 OUT_RING( R128_EVENT_CRTC_OFFSET ); \
517 #define OUT_RING( x ) do { \
519 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
|
| /src/sys/external/bsd/drm2/dist/drm/r128/ |
| r128_state.c | 61 OUT_RING(CCE_PACKET0(R128_AUX1_SC_LEFT, 3));
62 OUT_RING(boxes[0].x1);
63 OUT_RING(boxes[0].x2 - 1);
64 OUT_RING(boxes[0].y1);
65 OUT_RING(boxes[0].y2 - 1);
70 OUT_RING(CCE_PACKET0(R128_AUX2_SC_LEFT, 3));
71 OUT_RING(boxes[1].x1);
72 OUT_RING(boxes[1].x2 - 1);
73 OUT_RING(boxes[1].y1);
74 OUT_RING(boxes[1].y2 - 1)
[all...] |
| r128_drv.h | 479 OUT_RING(CCE_PACKET0(R128_WAIT_UNTIL, 0)); \
480 OUT_RING(R128_EVENT_CRTC_OFFSET); \
538 #define OUT_RING(x) do { \
540 DRM_INFO(" OUT_RING( 0x%08x ) at 0x%x\n", \
|
| /src/sys/external/bsd/drm2/dist/drm/i810/ |
| i810_dma.c | 475 OUT_RING(GFX_OP_COLOR_FACTOR);
476 OUT_RING(code[I810_CTXREG_CF1]);
478 OUT_RING(GFX_OP_STIPPLE);
479 OUT_RING(code[I810_CTXREG_ST1]);
486 OUT_RING(tmp);
493 OUT_RING(0);
507 OUT_RING(GFX_OP_MAP_INFO);
508 OUT_RING(code[I810_TEXREG_MI1]);
509 OUT_RING(code[I810_TEXREG_MI2]);
510 OUT_RING(code[I810_TEXREG_MI3])
[all...] |
