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    Searched refs:Offset0 (Results 1 - 11 of 11) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMHazardRecognizer.cpp 190 int64_t Offset0 = 0;
208 Ptr0 = GetPointerBaseWithConstantOffset(BaseVal0, Offset0, DL, true);
211 return CheckOffsets(Offset0, Offset1);
220 Offset0 = MF.getFrameInfo().getObjectOffset(FS0->getFrameIndex());
222 return CheckOffsets(Offset0, Offset1);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonSubtarget.cpp 347 int64_t Offset0;
349 MachineOperand *BaseOp0 = HII.getBaseAndOffset(L0, Offset0, Size0);
368 if (((Offset0 ^ Offset1) & 0x18) != 0)
HexagonISelLoweringHVX.cpp 1729 SDValue Offset0 = DAG.getTargetConstant(0, dl, ty(Base));
1733 {Mask, Base, Offset0, Value, Chain}, DAG);
1760 {MaskU.first, Base, Offset0, ValueU.first, Chain}, DAG);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUISelDAGToDAG.cpp 180 bool isDSOffset2Legal(SDValue Base, unsigned Offset0, unsigned Offset1,
183 bool SelectDS64Bit4ByteAligned(SDValue Ptr, SDValue &Base, SDValue &Offset0,
185 bool SelectDS128Bit8ByteAligned(SDValue Ptr, SDValue &Base, SDValue &Offset0,
187 bool SelectDSReadWrite2(SDValue Ptr, SDValue &Base, SDValue &Offset0,
1278 bool AMDGPUDAGToDAGISel::isDSOffset2Legal(SDValue Base, unsigned Offset0,
1281 if (Offset0 % Size != 0 || Offset1 % Size != 0)
1283 if (!isUInt<8>(Offset0 / Size) || !isUInt<8>(Offset1 / Size))
1297 SDValue &Offset0,
1299 return SelectDSReadWrite2(Addr, Base, Offset0, Offset1, 4);
1303 SDValue &Offset0,
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AMDGPUInstructionSelector.h 217 bool isDSOffset2Legal(Register Base, int64_t Offset0, int64_t Offset1,
SIInstrInfo.cpp 130 int64_t &Offset0,
166 Offset0 = cast<ConstantSDNode>(Load0->getOperand(Offset0Idx))->getZExtValue();
191 Offset0 = Load0Offset->getZExtValue();
224 Offset0 = cast<ConstantSDNode>(Off0)->getZExtValue();
274 // The 2 offset instructions use offset0 and offset1 instead. We can treat
278 getNamedOperand(LdSt, AMDGPU::OpName::offset0);
282 unsigned Offset0 = Offset0Op->getImm();
284 if (Offset0 + 1 != Offset1)
303 Offset = EltSize * Offset0;
471 int64_t Offset0, int64_t Offset1
    [all...]
AMDGPUInstructionSelector.cpp 1268 unsigned Offset0 = OrderedCountIndex << 2;
1275 unsigned Offset = Offset0 | (Offset1 << 8);
3792 bool AMDGPUInstructionSelector::isDSOffset2Legal(Register Base, int64_t Offset0,
3795 if (Offset0 % Size != 0 || Offset1 % Size != 0)
3797 if (!isUInt<8>(Offset0 / Size) || !isUInt<8>(Offset1 / Size))
SIInstrInfo.h 198 bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0,
SIISelLowering.cpp 6846 unsigned Offset0 = OrderedCountIndex << 2;
6853 unsigned Offset = Offset0 | (Offset1 << 8);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
DAGCombiner.cpp 15253 // x0 * offset0 + y0 * ptr0 = t0
15261 // t0 = (x0 * offset0 - x1 * y0 * y1 *offset1) + (y0 * y1) * t1
15264 const APInt &Offset0 = CN->getAPIntValue();
15273 APInt CNV = Offset0;
17384 int64_t Offset0 = LoadNodes[0].OffsetFromBase;
17387 if (Offset0 - Offset1 == ElementSizeBytes &&
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelLowering.cpp 7764 bool Offset0 = false, Offset1 = false;
7776 Offset0 = true;
7801 if (Offset0 || Offset1) {
7803 if ((Offset0 && isInRange(M, 0, NumElts)) ||
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