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    Searched refs:Op1VT (Results 1 - 3 of 3) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 14292 EVT Op1VT = N->getOperand(1).getValueType();
14300 (Op1VT == MVT::i32 || Op1VT == MVT::i64 ||
14301 (Subtarget.hasP9Vector() && (Op1VT == MVT::i16 || Op1VT == MVT::i8)));
14326 unsigned ByteSize = Op1VT.getScalarSizeInBits() / 8;
14329 DAG.getValueType(Op1VT) };
14729 EVT Op1VT = N->getOperand(1).getValueType();
14748 (Op1VT == MVT::i32 || Op1VT == MVT::i16 |
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 8645 EVT Op1VT = V1.getValueType();
8649 assert(Op1VT == Op2VT && "Operand types don't match!");
8655 SDValue NewV1 = PromoteMVEPredVector(dl, V1, Op1VT, DAG);
8722 EVT Op1VT = V1.getValueType();
8731 SDValue NewV1 = PromoteMVEPredVector(dl, V1, Op1VT, DAG);
9051 EVT Op1VT = Op1.getValueType();
9054 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
9056 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 3735 EVT Op1VT = Op1.getValueType();
3738 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
3740 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));

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