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    Searched refs:Op3 (Results 1 - 25 of 27) sorted by relevancy

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  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblySelectionDAGInfo.h 27 SDValue Op3, Align Alignment, bool isVolatile,
33 SDValue Op1, SDValue Op2, SDValue Op3,
39 SDValue Op3, Align Alignment, bool IsVolatile,
WebAssemblySelectionDAGInfo.cpp 38 SDValue Op3, Align Alignment, bool IsVolatile,
40 return EmitTargetCodeForMemcpy(DAG, DL, Chain, Op1, Op2, Op3,
  /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
XCoreSelectionDAGInfo.h 24 SDValue Op3, Align Alignment, bool isVolatile,
  /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/Disassembler/
XCoreDisassembler.cpp 259 unsigned &Op3) {
269 Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2);
538 unsigned Op1, Op2, Op3;
539 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
543 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
551 unsigned Op1, Op2, Op3;
552 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
556 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
564 unsigned Op1, Op2, Op3;
565 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
    [all...]
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
SelectionDAGTargetInfo.h 53 SDValue Op2, SDValue Op3,
69 SDValue Op2, SDValue Op3, Align Alignment, bool isVolatile,
82 SDValue Op2, SDValue Op3,
94 SDValue Op1, SDValue Op2, SDValue Op3,
SelectionDAG.h 1370 SDValue Op3);
1372 SDValue Op3, SDValue Op4);
1374 SDValue Op3, SDValue Op4, SDValue Op5);
1402 SDValue Op1, SDValue Op2, SDValue Op3);
1437 SDValue Op1, SDValue Op2, SDValue Op3);
1443 EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
1450 SDValue Op3);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMSelectionDAGInfo.h 57 SDValue Op3, Align Alignment, bool isVolatile,
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86InstrBuilder.h 110 const MachineOperand &Op3 = MI->getOperand(Operand + 3);
111 if (Op3.isGlobal())
112 AM.GV = Op3.getGlobal();
114 AM.Disp = Op3.getImm();
X86FastISel.cpp 178 unsigned Op1, unsigned Op2, unsigned Op3);
3956 unsigned Op2, unsigned Op3) {
3963 Op3 = constrainOperandRegClass(II, Op3, II.getNumDefs() + 3);
3970 .addReg(Op3);
3976 .addReg(Op3);
X86ISelDAGToDAG.cpp 5974 SDValue Op0, Op1, Op2, Op3, Op4;
5982 if (!selectAddr(nullptr, Op, Op0, Op1, Op2, Op3, Op4))
5990 OutOps.push_back(Op3);
  /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/AsmParser/
BPFAsmParser.cpp 271 BPFOperand &Op3 = (BPFOperand &)*Operands[3];
272 if (Op0.isReg() && Op1.isToken() && Op2.isToken() && Op3.isReg()
278 && Op0.getReg() != Op3.getReg())
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/
AArch64InstPrinter.cpp 78 const MCOperand &Op3 = MI->getOperand(3);
82 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) {
85 switch (Op3.getImm()) {
118 if (Op2.isImm() && Op3.isImm()) {
122 int64_t imms = Op3.getImm();
152 if (Op2.getImm() > Op3.getImm()) {
155 << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1;
163 << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/
AArch64AsmParser.cpp 4755 AArch64Operand &Op3 = static_cast<AArch64Operand &>(*Operands[3]);
4756 if (Op2.isScalarReg() && Op3.isImm()) {
4757 const MCConstantExpr *Op3CE = dyn_cast<MCConstantExpr>(Op3.getImm());
4777 NewOp4, Op3.getStartLoc(), Op3.getEndLoc(), getContext()));
4778 Operands[3] = AArch64Operand::CreateImm(NewOp3, Op3.getStartLoc(),
4779 Op3.getEndLoc(), getContext());
4841 AArch64Operand &Op3 = static_cast<AArch64Operand &>(*Operands[3]);
4844 if (Op1.isScalarReg() && Op3.isImm() && Op4.isImm()) {
4845 const MCConstantExpr *Op3CE = dyn_cast<MCConstantExpr>(Op3.getImm())
    [all...]
  /src/external/apache2/llvm/dist/llvm/include/llvm/IR/
PatternMatch.h 1454 T2 Op3;
1456 ThreeOps_match(const T0 &Op1, const T1 &Op2, const T2 &Op3)
1457 : Op1(Op1), Op2(Op2), Op3(Op3) {}
1463 Op3.match(I->getOperand(2));
2132 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2, const T3 &Op3) {
2133 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1, Op2), m_Argument<3>(Op3));
2139 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2, const T3 &Op3,
2141 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1, Op2, Op3),
2148 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2, const T3 &Op3,
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonInstrInfo.cpp 1257 const MachineOperand &Op3 = MI.getOperand(3);
1261 Register Rt = Op3.getReg();
1265 unsigned K3 = getKillRegState(Op3.isKill());
1281 const MachineOperand &Op3 = MI.getOperand(3);
1289 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1299 if (Op0.getReg() != Op3.getReg()) {
1303 .add(Op3);
1314 MachineOperand &Op3 = MI.getOperand(3);
1322 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1335 if (Op0.getReg() != Op3.getReg())
    [all...]
HexagonSplitDouble.cpp 905 MachineOperand &Op3 = MI->getOperand(3);
906 assert(Op0.isReg() && Op1.isReg() && Op2.isReg() && Op3.isImm());
907 int64_t Sh64 = Op3.getImm();
926 // Op0 = S2_asl_i_p_or Op1, Op2, Op3
927 // means: Op0 = or (Op1, asl(Op2, Op3))
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsTargetStreamer.h 137 MCOperand Op3, SMLoc IDLoc, const MCSubtargetInfo *STI);
MipsFastISel.cpp 237 unsigned Op3) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/
MipsTargetStreamer.cpp 227 unsigned Reg2, MCOperand Op3, SMLoc IDLoc,
234 TmpInst.addOperand(Op3);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
SelectionDAG.cpp 8207 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3) {
8208 SDValue Ops[] = { Op1, Op2, Op3 };
8214 SDValue Op3, SDValue Op4) {
8215 SDValue Ops[] = { Op1, Op2, Op3, Op4 };
8221 SDValue Op3, SDValue Op4, SDValue Op5) {
8222 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 };
8315 SDValue Op2, SDValue Op3) {
8317 SDValue Ops[] = { Op1, Op2, Op3 };
8522 SDValue Op3) {
8524 SDValue Ops[] = { Op1, Op2, Op3 };
    [all...]
SelectionDAGBuilder.cpp 5828 SDValue Op3 = getValue(I.getArgOperand(2));
5838 SDValue MC = DAG.getMemcpy(Root, sdl, Op1, Op2, Op3, Alignment, isVol,
5870 SDValue Op3 = getValue(I.getArgOperand(2));
5876 SDValue MS = DAG.getMemset(Root, sdl, Op1, Op2, Op3, Alignment, isVol, isTC,
5885 SDValue Op3 = getValue(I.getArgOperand(2));
5895 SDValue MM = DAG.getMemmove(Root, sdl, Op1, Op2, Op3, Alignment, isVol,
6459 SDValue Op3 = getValue(I.getArgOperand(2));
6461 Op1.getValueType(), Op1, Op2, Op3));
6470 SDValue Op3 = getValue(I.getArgOperand(2));
6472 Op1, Op2, Op3, DAG, TLI))
    [all...]
LegalizeIntegerTypes.cpp 307 // target's atomic operations. Op3 is merely stored and so can be left alone.
309 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
328 N->getBasePtr(), Op2, Op3, N->getMemOperand());
1981 SDValue Op3 = ZExtPromotedInteger(N->getOperand(3));
1984 Op2, Op3, Op4),
  /src/external/apache2/llvm/dist/llvm/lib/IR/
Verifier.cpp 5148 auto *Op3 = cast<ConstantInt>(Call.getArgOperand(2));
5149 Assert(Op3->getType()->getBitWidth() <= 32,
5155 Op3->getZExtValue() < Op1->getType()->getScalarSizeInBits(),
5159 Assert(Op3->getZExtValue() <= Op1->getType()->getScalarSizeInBits(),
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/
ARMAsmParser.cpp 6622 const auto &Op3 = static_cast<ARMOperand &>(*Operands[3]);
6624 if (!Op3.isReg() || !Op4.isReg())
6627 auto Op3Reg = Op3.getReg();
6945 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]);
6949 if (!Op3.isGPRMem())
7027 const MCParsedAsmOperand &Op3 = *Operands[3 + NumPredOps];
7028 if (!Op3.isReg() || Op3.getReg() != RNext)
7029 return Error(Op3.getStartLoc(), "operand must be a consecutive register");
  /src/external/apache2/llvm/dist/llvm/lib/Analysis/
ConstantFolding.cpp 2725 if (const auto *Op3 = dyn_cast<ConstantFP>(Operands[2])) {
2728 const APFloat &C3 = Op3->getValueAPF();

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