HomeSort by: relevance | last modified time | path
    Searched refs:Op5 (Results 1 - 5 of 5) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/Disassembler/
XCoreDisassembler.cpp 647 unsigned Op1, Op2, Op3, Op4, Op5, Op6;
652 S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6);
659 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
681 unsigned Op1, Op2, Op3, Op4, Op5;
686 S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5);
694 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/
ARMAsmParser.cpp 6634 auto &Op5 = static_cast<ARMOperand &>(*Operands[5]);
6639 (Op5.isReg() && Op5.getReg() == ARM::PC);
6642 (Op5.isReg() && Op5.getReg() == ARM::SP)) &&
6644 Op5.isImm() && !Op5.isImm0_508s4());
6663 // Op4 and Op5. The 'ADD Rdm, SP, Rdm' form is already handled specially
6665 const ARMOperand *LastOp = &Op5;
6667 if (!Transform && Op5.isReg() && Op3Reg == Op5.getReg() &
    [all...]
  /src/external/apache2/llvm/dist/llvm/include/llvm/IR/
PatternMatch.h 2149 const T4 &Op4, const T5 &Op5) {
2151 m_Argument<5>(Op5));
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
SelectionDAG.h 1374 SDValue Op3, SDValue Op4, SDValue Op5);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
SelectionDAG.cpp 8221 SDValue Op3, SDValue Op4, SDValue Op5) {
8222 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 };

Completed in 82 milliseconds