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    Searched refs:OpRC (Results 1 - 8 of 8) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
BreakFalseDeps.cpp 134 const TargetRegisterClass *OpRC =
141 !OpRC->contains(CurrMO.getReg()))
153 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC);
MachineInstr.cpp 951 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
957 if (OpRC)
958 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
961 } else if (OpRC)
962 CurRC = TRI->getCommonSubClass(CurRC, OpRC);
RegAllocFast.cpp 1064 const TargetRegisterClass *OpRC = MRI->getRegClass(Reg);
1069 if (OpRC->hasSubClassEq(IdxRC))
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86SpeculativeLoadHardening.cpp 1662 auto *OpRC = MRI->getRegClass(OpReg);
1663 Register TmpReg = MRI->createVirtualRegister(OpRC);
1667 if (!Subtarget->hasVLX() && (OpRC->hasSuperClassEq(&X86::VR128RegClass) ||
1668 OpRC->hasSuperClassEq(&X86::VR256RegClass))) {
1670 bool Is128Bit = OpRC->hasSuperClassEq(&X86::VR128RegClass);
1684 Register VBStateReg = MRI->createVirtualRegister(OpRC);
1704 } else if (OpRC->hasSuperClassEq(&X86::VR128XRegClass) ||
1705 OpRC->hasSuperClassEq(&X86::VR256XRegClass) ||
1706 OpRC->hasSuperClassEq(&X86::VR512RegClass)) {
1708 bool Is128Bit = OpRC->hasSuperClassEq(&X86::VR128XRegClass)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
InstrEmitter.cpp 320 const TargetRegisterClass *OpRC = nullptr;
322 OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF);
324 if (OpRC) {
326 = MRI->constrainRegClass(VReg, OpRC, MinRCSize);
328 OpRC = TRI->getAllocatableClass(OpRC);
329 assert(OpRC && "Constraints cannot be fulfilled for allocation");
330 Register NewVReg = MRI->createVirtualRegister(OpRC);
389 const TargetRegisterClass *OpRC =
396 if (OpRC && IIRC && OpRC != IIRC && Register::isVirtualRegister(VReg))
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIFixSGPRCopies.cpp 812 const TargetRegisterClass *OpRC =
814 if (!TRI->isSGPRClass(OpRC) && OpRC != &AMDGPU::VS_32RegClass &&
815 OpRC != &AMDGPU::VS_64RegClass) {
SIInstrInfo.cpp 5091 const TargetRegisterClass *OpRC = RI.getSubClassWithSubReg(
5095 if (DstRC == OpRC)
5400 const TargetRegisterClass *OpRC =
5402 if (RI.hasVectorRegisters(OpRC)) {
5403 VRC = OpRC;
5405 SRC = OpRC;
5462 const TargetRegisterClass *OpRC = MRI.getRegClass(Op.getReg());
5463 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(OpRC);
5464 if (VRC == OpRC)
6922 const TargetRegisterClass *OpRC = RI.getRegClass(Desc.OpInfo[Idx].RegClass)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonBitSimplify.cpp 1886 auto *OpRC = HII.getRegClass(HII.get(Opc), OpNum, &HRI, MF);
1888 return OpRC->hasSubClassEq(RRC);

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