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    Searched refs:OpReg (Results 1 - 15 of 15) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86FastISel.cpp 1742 Register OpReg = getRegForValue(TI->getOperand(0));
1743 if (OpReg == 0) return false;
1746 .addReg(OpReg).addImm(1);
1777 Register OpReg = getRegForValue(BI->getCondition());
1778 if (OpReg == 0) return false;
1780 // In case OpReg is a K register, COPY to a GPR
1781 if (MRI.getRegClass(OpReg) == &X86::VK1RegClass) {
1782 unsigned KOpReg = OpReg;
1783 OpReg = createResultReg(&X86::GR32RegClass);
1785 TII.get(TargetOpcode::COPY), OpReg)
    [all...]
X86SpeculativeLoadHardening.cpp 1661 Register OpReg = Op->getReg();
1662 auto *OpRC = MRI->getRegClass(OpReg);
1700 .addReg(OpReg);
1731 .addReg(OpReg);
1744 .addReg(OpReg);
1753 .addReg(OpReg)
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
A15SDOptimizer.cpp 298 Register OpReg = MI->getOperand(I).getReg();
300 if (!Register::isVirtualRegister(OpReg))
303 MachineInstr *Def = MRI->getVRegDef(OpReg);
ARMInstructionSelector.cpp 1043 Register OpReg = I.getOperand(2).getReg();
1044 unsigned Size = MRI.getType(OpReg).getSizeInBits();
ARMFastISel.cpp 1260 unsigned OpReg = getRegForValue(TI->getOperand(0));
1261 OpReg = constrainOperandRegClass(TII.get(TstOpc), OpReg, 0);
1264 .addReg(OpReg).addImm(1));
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPURegisterBankInfo.cpp 838 Register OpReg = Op.getReg();
839 LLT OpTy = MRI.getType(OpReg);
841 const RegisterBank *OpBank = getRegBank(OpReg, MRI, *TRI);
845 OpReg = B.buildCopy(OpTy, OpReg).getReg(0);
846 MRI.setRegBank(OpReg, AMDGPU::VGPRRegBank);
859 constrainGenericRegister(OpReg, AMDGPU::VGPR_32RegClass, MRI);
863 .addReg(OpReg);
874 .addReg(OpReg);
906 auto Unmerge = B.buildUnmerge(UnmergeTy, OpReg);
    [all...]
AMDGPUInstructionSelector.cpp 2205 Register OpReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
2216 BuildMI(*BB, &MI, DL, TII.get(Opc), OpReg)
2222 .addReg(OpReg)
2242 Register OpReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
2257 BuildMI(*BB, &MI, DL, TII.get(AMDGPU::S_AND_B32), OpReg)
2263 .addReg(OpReg)
SIInstrInfo.cpp 5088 Register OpReg = Op.getReg();
5092 RI.getRegClassForReg(MRI, OpReg), OpSubReg);
5105 MachineInstr *Def = MRI.getVRegDef(OpReg);
5111 FoldImmediate(*Copy, *Def, OpReg, &MRI);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
FastISel.cpp 1600 Register OpReg = getRegForValue(In);
1601 if (!OpReg)
1607 OpReg);
1622 ISD::BITCAST, OpReg);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
LegalizerHelper.cpp 3201 Register OpReg = MI.getOperand(1).getReg();
3205 MIRBuilder.buildAShr(DstTy, OpReg, ShiftAmt);
3206 auto Add = MIRBuilder.buildAdd(DstTy, OpReg, Shift);
4897 Register OpReg = MI.getOperand(0).getReg();
4899 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
4906 } else if (SrcStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
4912 // OpSegStart is where this destination segment would start in OpReg if it
4966 Register OpReg = MI.getOperand(2).getReg();
4968 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
4976 } else if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
MachineInstr.cpp 1951 Register OpReg = MO.getReg();
1952 if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg)
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/
MipsAsmParser.cpp 4541 unsigned OpReg = Inst.getOperand(2).getReg();
4557 // $SrcReg >= $OpReg is equal to (not ($SrcReg < $OpReg))
4558 TOut.emitRRR(OpCode, DstReg, SrcReg, OpReg, IDLoc, STI);
4678 unsigned OpReg = Inst.getOperand(2).getReg();
4694 // $SrcReg <= $OpReg is equal to (not ($OpReg < $SrcReg))
4695 TOut.emitRRR(OpCode, DstReg, OpReg, SrcReg, IDLoc, STI);
5369 unsigned OpReg = Inst.getOperand(2).getReg();
5373 if (SrcReg != Mips::ZERO && OpReg != Mips::ZERO)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/
X86InstComments.cpp 251 unsigned OpReg = MI->getOperand(OperandIndex).getReg();
252 return getVectorRegSize(OpReg) / ScalarSize;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64InstructionSelector.cpp 5991 Register OpReg = MO.getReg();
5992 const RegisterBank *RB = MRI.getRegBankOrNull(OpReg);
5995 auto *OpDef = MRI.getVRegDef(OpReg);
5996 const LLT &Ty = MRI.getType(OpReg);
5998 auto Copy = MIB.buildCopy(Ty, OpReg);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/
ARMAsmParser.cpp 7462 unsigned OpReg = Inst.getOperand(i).getReg();
7463 if (OpReg == Reg)
7466 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
7476 unsigned OpReg = Inst.getOperand(i).getReg();
7477 if (OpReg == Reg)

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