| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| RuntimeLibcalls.h | 38 Libcall getFPEXT(EVT OpVT, EVT RetVT);
42 Libcall getFPROUND(EVT OpVT, EVT RetVT);
46 Libcall getFPTOSINT(EVT OpVT, EVT RetVT);
50 Libcall getFPTOUINT(EVT OpVT, EVT RetVT);
54 Libcall getSINTTOFP(EVT OpVT, EVT RetVT);
58 Libcall getUINTTOFP(EVT OpVT, EVT RetVT);
|
| SelectionDAG.h | 651 /// BooleanContent for type \p OpVT.
652 SDValue getBoolConstant(bool V, const SDLoc &DL, EVT VT, EVT OpVT);
883 /// BooleanContent for type OpVT or truncating it.
884 SDValue getBoolExtOrTrunc(SDValue Op, const SDLoc &SL, EVT VT, EVT OpVT);
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | 216 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
217 if (OpVT == MVT::f16) {
224 } else if (OpVT == MVT::f32) {
231 } else if (OpVT == MVT::f64) {
236 } else if (OpVT == MVT::f80) {
246 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
248 if (OpVT == MVT::f32)
250 if (OpVT == MVT::f64)
252 if (OpVT == MVT::f80)
254 if (OpVT == MVT::f128
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeFloatTypes.cpp | 165 EVT OpVT = N->getOperand(0 + Offset).getValueType();
166 CallOptions.setTypeListBeforeSoften(OpVT, N->getValueType(0), true);
514 EVT OpVT = N->getOperand(IsStrict ? 1 : 0).getValueType();
515 CallOptions.setTypeListBeforeSoften(OpVT, N->getValueType(0), true);
551 EVT OpVT = N->getOperand(IsStrict ? 1 : 0).getValueType();
552 CallOptions.setTypeListBeforeSoften(OpVT, N->getValueType(0), true);
1095 EVT OpVT = N->getOperand(0 + Offset).getValueType();
1096 CallOptions.setTypeListBeforeSoften(OpVT, N->getValueType(0), true);
1110 EVT OpVT = N->getOperand(N->isStrictFPOpcode() ? 1 : 0).getValueType();
1111 return SoftenFloatOp_Unary(N, GetFPLibCall(OpVT,
[all...] |
| SelectionDAG.cpp | 1281 EVT OpVT) {
1285 TargetLowering::BooleanContent BType = TLI->getBooleanContents(OpVT);
1290 EVT OpVT = Op.getValueType();
1291 assert(VT.isInteger() && OpVT.isInteger() &&
1293 assert(VT.isVector() == OpVT.isVector() &&
1297 VT.getVectorElementCount() == OpVT.getVectorElementCount()) &&
1299 assert(VT.bitsLE(OpVT) && "Not extending!");
1300 if (OpVT == VT)
1302 APInt Imm = APInt::getLowBitsSet(OpVT.getScalarSizeInBits(),
1304 return getNode(ISD::AND, DL, OpVT, Op, getConstant(Imm, DL, OpVT))
[all...] |
| TargetLowering.cpp | 3150 EVT OpVT = N0.getValueType();
3151 if (N0.getOpcode() != ISD::AND || !OpVT.isInteger() ||
3167 SDValue Zero = DAG.getConstant(0, DL, OpVT);
3173 assert(OpVT.isInteger());
3174 Cond = ISD::getSetCCInverse(Cond, OpVT);
3192 SDValue NotX = DAG.getNOT(SDLoc(X), X, OpVT);
3193 SDValue NewAnd = DAG.getNode(ISD::AND, SDLoc(N0), OpVT, NotX, Y);
3384 EVT OpVT = N0.getValueType();
3388 return DAG.getSetCC(DL, VT, Y, DAG.getConstant(0, DL, OpVT), Cond);
3396 return DAG.getSetCC(DL, VT, X, DAG.getConstant(0, DL, OpVT), Cond)
[all...] |
| ScheduleDAGSDNodes.cpp | 483 EVT OpVT = N->getOperand(i).getValueType();
484 assert(OpVT != MVT::Glue && "Glued nodes should be in same sunit!");
485 bool isChain = OpVT == MVT::Other;
|
| LegalizeVectorTypes.cpp | 323 EVT OpVT = Op.getValueType();
326 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
329 EVT VT = OpVT.getVectorElementType();
375 EVT OpVT = Op.getValueType();
384 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
387 EVT VT = OpVT.getVectorElementType();
406 EVT OpVT = Op.getValueType();
407 EVT OpEltVT = OpVT.getVectorElementType();
410 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
441 EVT OpVT = Cond.getValueType()
[all...] |
| LegalizeVectorOps.cpp | 499 MVT OpVT = Node->getOperand(0).getSimpleValueType();
501 Action = TLI.getCondCodeAction(CCCode, OpVT);
1354 MVT OpVT = Node->getOperand(0).getSimpleValueType();
1357 if (TLI.getCondCodeAction(CCCode, OpVT) != TargetLowering::Expand) {
|
| LegalizeTypes.cpp | 307 EVT OpVT = Op.getValueType();
308 switch (getTypeAction(OpVT)) {
|
| InstrEmitter.cpp | 385 MVT OpVT = Op.getSimpleValueType();
390 TLI->isTypeLegal(OpVT)
391 ? TLI->getRegClassFor(OpVT,
|
| DAGCombiner.cpp | 4963 EVT OpVT = LL.getValueType();
4965 if (VT != getSetCCResultType(OpVT))
4967 if (OpVT != RL.getValueType())
4972 bool IsInteger = OpVT.isInteger();
4991 SDValue Or = DAG.getNode(ISD::OR, SDLoc(N0), OpVT, LL, RL);
5010 SDValue And = DAG.getNode(ISD::AND, SDLoc(N0), OpVT, LL, RL);
5018 if (IsAnd && LL == RL && CC0 == CC1 && OpVT.getScalarSizeInBits() > 1 &&
5022 SDValue One = DAG.getConstant(1, DL, OpVT);
5023 SDValue Two = DAG.getConstant(2, DL, OpVT);
5024 SDValue Add = DAG.getNode(ISD::ADD, SDLoc(N0), OpVT, LL, One)
[all...] |
| LegalizeDAG.cpp | 1045 MVT OpVT = Node->getOperand(CompareOperand).getSimpleValueType();
1048 Action = TLI.getCondCodeAction(CCCode, OpVT);
1054 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
1860 EVT OpVT = Node->getOperand(0).getValueType();
1902 if (OpVT==EltVT)
1905 // If OpVT and EltVT don't match, EltVT is not legal and the
|
| LegalizeIntegerTypes.cpp | 1764 EVT OpVT = N->getOpcode() == ISD::SELECT ? OpTy.getScalarType() : OpTy;
1765 Cond = PromoteTargetBoolean(Cond, OpVT);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 2369 EVT OpVT = Op.getOperand(0).getValueType();
2370 assert(OpVT == MVT::i32 || (OpVT == MVT::i64));
2372 EVT floatVT = (OpVT == MVT::i32) ? MVT::f32 : MVT::f64;
2376 && (!hasHardQuad || !TLI.isTypeLegal(OpVT))) {
2377 const char *libName = TLI.getLibcallName(OpVT == MVT::i32
2384 if (!TLI.isTypeLegal(OpVT))
2389 unsigned opcode = (OpVT == MVT::i32)? SPISD::ITOF : SPISD::XTOF;
2418 EVT OpVT = Op.getOperand(0).getValueType();
2419 assert(OpVT == MVT::i32 || OpVT == MVT::i64)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 6139 EVT OpVT = Op.getValueType();
6140 unsigned NumSubElts = OpVT.getVectorNumElements() / NumSubs;
6141 unsigned SizeSub = OpVT.getSizeInBits() / NumSubs;
6166 MVT OpVT = Op.getSimpleValueType();
6167 unsigned NumElems = OpVT.getVectorNumElements();
6171 MVT WideOpVT = OpVT;
6182 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, Op, ZeroIdx);
6205 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, Op, ZeroIdx);
6215 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, SubVec, ZeroIdx);
6228 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, SubVec, ZeroIdx)
[all...] |
| X86ISelDAGToDAG.cpp | 537 EVT OpVT = N->getOperand(0).getValueType();
541 OpVT = N->getOperand(1).getValueType();
542 if (OpVT.is256BitVector() || OpVT.is128BitVector())
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| R600ISelLowering.cpp | 1836 EVT OpVT = Ops[0].getValueType();
1837 if (InVal.getValueType() != OpVT)
1838 InVal = OpVT.bitsGT(InVal.getValueType()) ?
1839 DAG.getNode(ISD::ANY_EXTEND, DL, OpVT, InVal) :
1840 DAG.getNode(ISD::TRUNCATE, DL, OpVT, InVal);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonISelDAGToDAG.cpp | 1169 EVT OpVT = OpI1.getValueType();
1170 if (!OpVT.isSimple() || OpVT.getSimpleVT() != MVT::i1)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVISelLowering.cpp | 3267 MVT OpVT = ScalarOp.getSimpleValueType();
3271 if (!OpVT.isScalarInteger() || OpVT == XLenVT)
3275 if (OpVT.bitsLT(XLenVT)) {
3296 assert(XLenVT == MVT::i32 && OpVT == MVT::i64 &&
4330 MVT OpVT = V.getSimpleValueType();
4331 MVT ContainerVT = getContainerForFixedLengthVector(OpVT);
4332 assert(useRVVForFixedLengthVectorVT(OpVT) &&
4647 EVT OpVT = Op0.getValueType();
4648 CallOptions.setTypeListBeforeSoften(OpVT, N->getValueType(0), true)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 3462 EVT OpVT = Op.getValueType();
3464 if (useSVEForFixedLengthVectorVT(OpVT))
3467 if (OpVT != MVT::f16 && OpVT != MVT::bf16)
3476 DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, OpVT, Op,
10339 EVT OpVT = Op.getOperand(0).getValueType();
10340 SDValue Zero = DAG.getConstant(0, dl, OpVT);
10341 SDValue One = DAG.getConstant(1, dl, OpVT);
10342 SDValue And = DAG.getNode(ISD::AND, dl, OpVT, Op.getOperand(0), One);
17761 EVT OpVT = Op.getValueType()
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 5743 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
5745 Mask = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT,
5746 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
5753 Tmp1 = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT,
5754 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
5760 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
5761 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
5766 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
5767 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
5769 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
[all...] |
| /src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| CodeGenDAGPatterns.cpp | 2485 MVT::SimpleValueType OpVT = Int->IS.ParamVTs[i];
2487 MadeChange |= getChild(i+1)->UpdateNodeType(0, OpVT, TP);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 5765 EVT OpVT = Op.getValueType();
5766 unsigned OpBytesPerElement = OpVT.getVectorElementType().getStoreSize();
5795 EVT OpVT = Op.getOperand(0).getValueType();
5797 unsigned OpBytesPerElement = OpVT.getVectorElementType().getStoreSize();
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 13575 EVT OpVT = LHS.getValueType();
13576 SDValue Add = DAG.getNode(ISD::ADD, DL, OpVT, LHS, RHS.getOperand(1));
13577 return DAG.getSetCC(DL, VT, Add, DAG.getConstant(0, DL, OpVT), CC);
|
