| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| TargetOpcodes.h | 28 /// Check whether the given Opcode is a generic opcode that is not supposed
30 inline bool isPreISelGenericOpcode(unsigned Opcode) {
31 return Opcode >= TargetOpcode::PRE_ISEL_GENERIC_OPCODE_START &&
32 Opcode <= TargetOpcode::PRE_ISEL_GENERIC_OPCODE_END;
35 /// Check whether the given Opcode is a target-specific opcode.
36 inline bool isTargetSpecificOpcode(unsigned Opcode) {
37 return Opcode > TargetOpcode::PRE_ISEL_GENERIC_OPCODE_END;
40 /// \returns true if \p Opcode is an optimization hint opcode which is no
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/MC/ |
| MCInstrInfo.cpp | 17 unsigned Opcode = MI.getOpcode();
18 if (ComplexDeprecationInfos && ComplexDeprecationInfos[Opcode])
19 return ComplexDeprecationInfos[Opcode](MI, STI, Info);
20 if (DeprecatedFeatures && DeprecatedFeatures[Opcode] != uint8_t(-1U) &&
21 STI.getFeatureBits()[DeprecatedFeatures[Opcode]]) {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/TargetInfo/ |
| WebAssemblyTargetInfo.h | 26 int getStackOpcode(unsigned short Opcode);
27 int getWasm64Opcode(unsigned short Opcode);
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/MC/ |
| MCInstrInfo.h | 61 /// specified instruction opcode.
62 const MCInstrDesc &get(unsigned Opcode) const {
63 assert(Opcode < NumOpcodes && "Invalid opcode!");
64 return Desc[Opcode];
67 /// Returns the name for the instructions with the given opcode.
68 StringRef getName(unsigned Opcode) const {
69 assert(Opcode < NumOpcodes && "Invalid opcode!");
70 return StringRef(&InstrNameData[InstrNameIndices[Opcode]]);
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCPredicates.h | 70 Predicate InvertPredicate(Predicate Opcode);
74 Predicate getSwappedPredicate(Predicate Opcode);
77 inline unsigned getPredicateCondition(Predicate Opcode) {
78 return (unsigned)(Opcode & ~BR_HINT_MASK);
82 inline unsigned getPredicateHint(Predicate Opcode) {
83 return (unsigned)(Opcode & BR_HINT_MASK);
|
| /src/external/apache2/llvm/dist/clang/lib/AST/Interp/ |
| Opcode.h | 1 //===--- Opcode.h - Opcodes for the constexpr VM ----------------*- C++ -*-===//
21 enum Opcode : uint32_t {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMUnwindOpAsm.h | 9 // This file declares the unwind opcode assembler for ARM exception handling
36 /// Reset the unwind opcode assembler.
67 /// Finalize the unwind opcode sequence for emitBytes()
72 void EmitInt8(unsigned Opcode) {
73 Ops.push_back(Opcode & 0xff);
77 void EmitInt16(unsigned Opcode) {
78 Ops.push_back((Opcode >> 8) & 0xff);
79 Ops.push_back(Opcode & 0xff);
83 void emitBytes(const uint8_t *Opcode, size_t Size) {
84 Ops.insert(Ops.end(), Opcode, Opcode + Size)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| BPFMISimplifyPatchable.cpp | 71 unsigned Opcode);
109 unsigned Opcode = DefInst->getOpcode();
111 if (Opcode == BPF::LDB || Opcode == BPF::LDH || Opcode == BPF::LDW ||
112 Opcode == BPF::LDD || Opcode == BPF::STB || Opcode == BPF::STH ||
113 Opcode == BPF::STW || Opcode == BPF::STD
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ExpandImm.h | 23 unsigned Opcode;
|
| /src/sys/external/bsd/acpica/dist/parser/ |
| psutils.c | 89 * Opcode - Opcode to store in the Op
100 UINT16 Opcode)
106 Op->Common.AmlOpcode = Opcode;
109 (AcpiPsGetOpcodeInfo (Opcode))->Name,
118 * PARAMETERS: Opcode - Opcode that will be stored in the new Op
119 * Aml - Address of the opcode
124 * opcode. A cache of opcodes is available for the pure
131 UINT16 Opcode,
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SIInstrInfo.h | 59 static BranchPredicate getBranchPredicate(unsigned Opcode);
92 unsigned Opcode) const;
96 unsigned Opcode) const;
99 MachineInstr &Inst, unsigned Opcode,
106 unsigned Opcode,
235 // Splits a V_MOV_B64_DPP_PSEUDO opcode into a pair of v_mov_b32_dpp
243 // Returns an opcode that can be used to move a value to a \p DstRC
343 bool isSALU(uint16_t Opcode) const {
344 return get(Opcode).TSFlags & SIInstrFlags::SALU;
351 bool isVALU(uint16_t Opcode) const
[all...] |
| R600InstrInfo.h | 81 bool isReductionOp(unsigned opcode) const;
82 bool isCubeOp(unsigned opcode) const;
84 /// \returns true if this \p Opcode represents an ALU instruction.
85 bool isALUInstr(unsigned Opcode) const;
86 bool hasInstrModifiers(unsigned Opcode) const;
87 bool isLDSInstr(unsigned Opcode) const;
88 bool isLDSRetInstr(unsigned Opcode) const;
90 /// \returns true if this \p Opcode represents an ALU instruction or an
94 bool isTransOnly(unsigned Opcode) const;
96 bool isVectorOnly(unsigned Opcode) const
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZTargetTransformInfo.cpp | 66 InstructionCost SystemZTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx,
81 switch (Opcode) {
384 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
392 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info,
413 Opcode == Instruction::SDiv || Opcode == Instruction::SRem;
415 Opcode == Instruction::UDiv || Opcode == Instruction::URem;
438 if (Opcode == Instruction::FAdd || Opcode == Instruction::FSub |
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| LeonPasses.cpp | 49 unsigned Opcode = MI.getOpcode();
50 if (Opcode >= SP::LDDArr && Opcode <= SP::LDrr) {
84 unsigned Opcode = MI.getOpcode();
85 if (Opcode == SP::CALL && MI.getNumOperands() > 0) {
136 unsigned Opcode = MI.getOpcode();
142 if (Opcode == SP::FSQRTD || Opcode == SP::FDIVD) {
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/IR/ |
| Instruction.h | 177 static const char* getOpcodeName(unsigned OpCode);
179 static inline bool isTerminator(unsigned OpCode) {
180 return OpCode >= TermOpsBegin && OpCode < TermOpsEnd;
183 static inline bool isUnaryOp(unsigned Opcode) {
184 return Opcode >= UnaryOpsBegin && Opcode < UnaryOpsEnd;
186 static inline bool isBinaryOp(unsigned Opcode) {
187 return Opcode >= BinaryOpsBegin && Opcode < BinaryOpsEnd
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsMCNaCl.h | 20 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCTargetTransformInfo.cpp | 235 InstructionCost PPCTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx,
240 return BaseT::getIntImmCostInst(Opcode, Idx, Imm, Ty, CostKind, Inst);
251 switch (Opcode) {
426 unsigned Opcode = 0;
494 case Intrinsic::fma: Opcode = ISD::FMA; break;
495 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
496 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
497 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
498 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
499 case Intrinsic::rint: Opcode = ISD::FRINT; break
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVTargetTransformInfo.cpp | 33 InstructionCost RISCVTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx,
49 switch (Opcode) {
75 if (Instruction::isCommutative(Opcode) || Idx == ImmArgIdx) {
134 unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask,
137 return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
140 if ((Opcode == Instruction::Load &&
142 (Opcode == Instruction::Store &&
144 return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
149 return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
155 getMemoryOpCost(Opcode, VTy->getElementType(), Alignment, 0, CostKind, I)
[all...] |
| /src/sys/external/bsd/acpica/dist/executer/ |
| exmisc.c | 154 * PARAMETERS: Opcode - AML opcode
160 * DESCRIPTION: Execute a math AML opcode. The purpose of having all of the
168 UINT16 Opcode,
176 switch (Opcode)
245 * PARAMETERS: Opcode - AML opcode
252 * DESCRIPTION: Execute a logical "Numeric" AML opcode. For these Numeric
263 UINT16 Opcode,
275 switch (Opcode)
[all...] |
| exoparg3.c | 68 * required for this opcode type (1 through 6 args).
70 * for this opcode type (0, 1, or 2 targets).
71 * zR - RETURN VALUE: Indicates whether this opcode type returns a value
100 AcpiPsGetOpcodeName (WalkState->Opcode));
103 switch (WalkState->Opcode)
127 * The alstests require that the Fatal() opcode does not return an error.
134 * If the interpreter sees this opcode, just ignore it. The External
136 * disassemble control method invocations. The opcode or group of
138 * AML interpreters never see the opcode. Thus, something is
139 * wrong if an external opcode ever gets here
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86AvoidStoreForwardingBlocks.cpp | 133 static bool isXMMLoadOpcode(unsigned Opcode) {
134 return Opcode == X86::MOVUPSrm || Opcode == X86::MOVAPSrm ||
135 Opcode == X86::VMOVUPSrm || Opcode == X86::VMOVAPSrm ||
136 Opcode == X86::VMOVUPDrm || Opcode == X86::VMOVAPDrm ||
137 Opcode == X86::VMOVDQUrm || Opcode == X86::VMOVDQArm ||
138 Opcode == X86::VMOVUPSZ128rm || Opcode == X86::VMOVAPSZ128rm |
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/DebugInfo/DWARF/ |
| DWARFExpression.cpp | 111 static DWARFExpression::Operation::Description getOpDesc(unsigned OpCode) {
115 if (OpCode >= Descriptions.size())
117 return Descriptions[OpCode];
124 Opcode = Data.getU8(&Offset);
126 Desc = getOpDesc(Opcode);
228 DIDumpOptions DumpOpts, uint8_t Opcode,
237 if (Opcode == DW_OP_bregx || Opcode == DW_OP_regx ||
238 Opcode == DW_OP_regval_type)
240 else if (Opcode >= DW_OP_breg0 && Opcode < DW_OP_bregx
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyTargetTransformInfo.cpp | 54 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
62 Opcode, Ty, CostKind, Opd1Info, Opd2Info, Opd1PropInfo, Opd2PropInfo);
65 switch (Opcode) {
77 getArithmeticInstrCost(Opcode, VTy->getElementType(), CostKind) +
85 InstructionCost WebAssemblyTTIImpl::getVectorInstrCost(unsigned Opcode,
89 BasicTTIImplBase::getVectorInstrCost(Opcode, Val, Index);
|
| /src/sys/external/bsd/acpica/dist/tools/acpihelp/ |
| ahaml.c | 3 * Module Name: ahaml - AML opcode decoding for acpihelp utility
60 * FUNCTION: AhFindAmlOpcode (entry point for AML opcode name search)
62 * PARAMETERS: Name - Name or prefix for an AML opcode.
82 /* Find/display all opcode names that match the input name prefix */
98 /* Upper case the opcode name before substring compare */
119 * FUNCTION: AhDecodeAmlOpcode (entry point for AML opcode search)
121 * PARAMETERS: OpcodeString - String version of AML opcode
125 * DESCRIPTION: Display information about the input AML opcode
134 UINT32 Opcode;
144 Opcode = strtoul (OpcodeString, NULL, 16)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonTargetTransformInfo.cpp | 159 InstructionCost HexagonTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src,
164 assert(Opcode == Instruction::Load || Opcode == Instruction::Store);
169 if (Opcode == Instruction::Store)
170 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
211 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
216 HexagonTTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *Src,
219 return BaseT::getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
230 unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask,
232 return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask
[all...] |
