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    Searched refs:Opcodes (Results 1 - 25 of 53) sorted by relevancy

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  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86InstrFMA3Info.h 10 // about existing X86 FMA3 opcodes, classifying and grouping them.
21 /// This class is used to group {132, 213, 231} forms of FMA opcodes together.
22 /// Each of the groups has either 3 opcodes, Also, each group has an attributes
25 /// An array holding 3 forms of FMA opcodes.
26 uint16_t Opcodes[3];
29 /// FMA groups of opcodes.
40 /// group of FMA opcodes consists of FMA intrinsic opcodes.
44 /// group of FMA opcodes consists of AVX512 opcodes accepting a k-mask an
    [all...]
X86InstrFMA3Info.cpp 10 // about existing X86 FMA3 opcodes, classifying and grouping them.
126 /// Returns a reference to a group of FMA3 opcodes to where the given
159 return Group.Opcodes[FormIndex] < Opcode;
161 assert(I != Table.end() && I->Opcodes[FormIndex] == Opcode &&
  /src/external/apache2/llvm/dist/llvm/tools/llvm-readobj/
ARMWinEHPrinter.h 38 bool opcode_0xxxxxxx(const uint8_t *Opcodes, unsigned &Offset,
40 bool opcode_10Lxxxxx(const uint8_t *Opcodes, unsigned &Offset,
42 bool opcode_1100xxxx(const uint8_t *Opcodes, unsigned &Offset,
44 bool opcode_11010Lxx(const uint8_t *Opcodes, unsigned &Offset,
46 bool opcode_11011Lxx(const uint8_t *Opcodes, unsigned &Offset,
48 bool opcode_11100xxx(const uint8_t *Opcodes, unsigned &Offset,
50 bool opcode_111010xx(const uint8_t *Opcodes, unsigned &Offset,
52 bool opcode_1110110L(const uint8_t *Opcodes, unsigned &Offset,
54 bool opcode_11101110(const uint8_t *Opcodes, unsigned &Offset,
56 bool opcode_11101111(const uint8_t *Opcodes, unsigned &Offset
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ARMEHABIPrinter.h 34 void (OpcodeDecoder::*Routine)(const uint8_t *Opcodes, unsigned &OI);
38 void Decode_00xxxxxx(const uint8_t *Opcodes, unsigned &OI);
39 void Decode_01xxxxxx(const uint8_t *Opcodes, unsigned &OI);
40 void Decode_1000iiii_iiiiiiii(const uint8_t *Opcodes, unsigned &OI);
41 void Decode_10011101(const uint8_t *Opcodes, unsigned &OI);
42 void Decode_10011111(const uint8_t *Opcodes, unsigned &OI);
43 void Decode_1001nnnn(const uint8_t *Opcodes, unsigned &OI);
44 void Decode_10100nnn(const uint8_t *Opcodes, unsigned &OI);
45 void Decode_10101nnn(const uint8_t *Opcodes, unsigned &OI);
46 void Decode_10110000(const uint8_t *Opcodes, unsigned &OI)
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  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/
ARMUnwindOpAsm.h 1 //===-- ARMUnwindOpAsm.h - ARM Unwind Opcodes Assembler ---------*- C++ -*-===//
49 /// Emit unwind opcodes for .save directives
52 /// Emit unwind opcodes for .vsave directives
55 /// Emit unwind opcodes to copy address from source register to $sp.
58 /// Emit unwind opcodes to add $sp with an offset.
61 /// Emit unwind raw opcodes
62 void EmitRaw(const SmallVectorImpl<uint8_t> &Opcodes) {
63 Ops.insert(Ops.end(), Opcodes.begin(), Opcodes.end());
64 OpBegins.push_back(OpBegins.back() + Opcodes.size())
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ARMELFStreamer.cpp 88 const SmallVectorImpl<uint8_t> &Opcodes) override;
266 const SmallVectorImpl<uint8_t> &Opcodes) {
268 for (SmallVectorImpl<uint8_t>::const_iterator OCI = Opcodes.begin(),
269 OCE = Opcodes.end();
392 const SmallVectorImpl<uint8_t> &Opcodes) override;
460 void emitUnwindRaw(int64_t Offset, const SmallVectorImpl<uint8_t> &Opcodes);
722 SmallVector<uint8_t, 64> Opcodes;
767 const SmallVectorImpl<uint8_t> &Opcodes) {
768 getStreamer().emitUnwindRaw(Offset, Opcodes);
1268 Opcodes.clear()
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  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMInstructionSelector.cpp 84 // Store the opcodes that we might need, so we don't have to check what kind
128 } const Opcodes;
175 TRI(*STI.getRegisterInfo()), TM(TM), RBI(RBI), STI(STI), Opcodes(STI),
347 return Size == 8 ? Opcodes.SEXT8 : Opcodes.SEXT16;
350 return Size == 8 ? Opcodes.ZEXT8 : Opcodes.ZEXT16;
364 return isStore ? Opcodes.STORE8 : Opcodes.LOAD8;
366 return isStore ? Opcodes.STORE16 : Opcodes.LOAD16
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ARMISelDAGToDAG.cpp 236 void SelectMVE_WB(SDNode *N, const uint16_t *Opcodes, bool Predicated);
256 /// opcodes for each element width.
274 /// pointer points to a set of NumVecs sub-opcodes used for the
277 const uint16_t *const *Opcodes, bool HasWriteback);
279 /// SelectMVE_VxDUP - Select MVE incrementing-dup instructions. Opcodes is an
281 void SelectMVE_VxDUP(SDNode *N, const uint16_t *Opcodes,
2530 void ARMDAGToDAGISel::SelectMVE_WB(SDNode *N, const uint16_t *Opcodes,
2538 Opcode = Opcodes[0];
2541 Opcode = Opcodes[1];
2692 const uint16_t *Opcodes = IsUnsigned ? OpcodesU : OpcodesS
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  /src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/
SerialSnippetGenerator.cpp 42 std::vector<unsigned> Opcodes;
43 Opcodes.resize(State.getInstrInfo().getNumOpcodes());
44 std::iota(Opcodes.begin(), Opcodes.end(), 0U);
45 llvm::shuffle(Opcodes.begin(), Opcodes.end(), randomGenerator());
48 for (const unsigned OtherOpcode : Opcodes) {
  /src/external/gpl3/gdb.old/dist/sim/d10v/
gencode.c 85 long Opcodes[512];
94 if (Opcodes[i] == op)
95 fprintf(stderr,"DUPLICATE OPCODES: %lx\n", op);
120 Opcodes[curop++] = opcode->opcode;
  /src/external/gpl3/gdb/dist/sim/d10v/
gencode.c 85 long Opcodes[512];
94 if (Opcodes[i] == op)
95 fprintf(stderr,"DUPLICATE OPCODES: %lx\n", op);
120 Opcodes[curop++] = opcode->opcode;
  /src/external/apache2/llvm/dist/llvm/tools/llvm-objcopy/MachO/
MachOWriter.cpp 54 assert((DyLdInfoCommand.rebase_size == O.Rebases.Opcodes.size()) &&
55 "Incorrect rebase opcodes size");
59 assert((DyLdInfoCommand.bind_size == O.Binds.Opcodes.size()) &&
60 "Incorrect bind opcodes size");
64 assert((DyLdInfoCommand.weak_bind_size == O.WeakBinds.Opcodes.size()) &&
65 "Incorrect weak bind opcodes size");
70 assert((DyLdInfoCommand.lazy_bind_size == O.LazyBinds.Opcodes.size()) &&
71 "Incorrect lazy bind opcodes size");
335 assert((DyLdInfoCommand.rebase_size == O.Rebases.Opcodes.size()) &&
336 "Incorrect rebase opcodes size")
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MachOLayoutBuilder.cpp 246 uint64_t StartOfBindingInfo = StartOfRebaseInfo + O.Rebases.Opcodes.size();
247 uint64_t StartOfWeakBindingInfo = StartOfBindingInfo + O.Binds.Opcodes.size();
249 StartOfWeakBindingInfo + O.WeakBinds.Opcodes.size();
251 StartOfLazyBindingInfo + O.LazyBinds.Opcodes.size();
331 O.Rebases.Opcodes.empty() ? 0 : StartOfRebaseInfo;
332 MLC.dyld_info_command_data.rebase_size = O.Rebases.Opcodes.size();
334 O.Binds.Opcodes.empty() ? 0 : StartOfBindingInfo;
335 MLC.dyld_info_command_data.bind_size = O.Binds.Opcodes.size();
337 O.WeakBinds.Opcodes.empty() ? 0 : StartOfWeakBindingInfo;
338 MLC.dyld_info_command_data.weak_bind_size = O.WeakBinds.Opcodes.size()
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Object.h 205 /// a stream of byte sized opcodes whose symbolic names start with
208 /// The opcodes are a compressed way to encode the table by only
215 ArrayRef<uint8_t> Opcodes;
221 /// images. The bind information is a stream of byte sized opcodes whose
224 /// symbol-name, addend> The opcodes are a compressed way to encode the table by
231 ArrayRef<uint8_t> Opcodes;
249 ArrayRef<uint8_t> Opcodes;
255 /// lazy_bind contains a stream of BIND opcodes to bind all lazy symbols. Normal
262 ArrayRef<uint8_t> Opcodes;
MachOReader.cpp 242 O.Rebases.Opcodes = MachOObj.getDyldInfoRebaseOpcodes();
246 O.Binds.Opcodes = MachOObj.getDyldInfoBindOpcodes();
250 O.WeakBinds.Opcodes = MachOObj.getDyldInfoWeakBindOpcodes();
254 O.LazyBinds.Opcodes = MachOObj.getDyldInfoLazyBindOpcodes();
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
PredicateExpander.cpp 118 const RecVec &Opcodes) {
119 assert(!Opcodes.empty() && "Expected at least one opcode to check!");
122 if (Opcodes.size() == 1) {
124 expandCheckOpcode(OS, Opcodes[0]);
131 for (const Record *Rec : Opcodes) {
148 const RecVec &Opcodes) {
152 expandCheckOpcode(OS, Opcodes);
242 const RecVec &Opcodes = Rec->getValueAsListOfDefs("Opcodes");
243 for (const Record *Opcode : Opcodes) {
    [all...]
PredicateExpander.h 72 void expandCheckPseudo(raw_ostream &OS, const RecVec &Opcodes);
73 void expandCheckOpcode(raw_ostream &OS, const RecVec &Opcodes);
CodeGenSchedule.h 355 std::vector<const Record *> Opcodes;
365 assert(!llvm::is_contained(Opcodes, Opcode) && "Opcode already in set!");
366 Opcodes.push_back(Opcode);
369 ArrayRef<const Record *> getOpcodes() const { return Opcodes; }
  /src/external/gpl3/gdb.old/dist/sim/cr16/
gencode.c 113 long Opcodes[512];
124 if (Opcodes[i] == op)
125 fprintf(stderr,"DUPLICATE OPCODES: %lx\n", op);
  /src/external/gpl3/gdb/dist/sim/cr16/
gencode.c 113 long Opcodes[512];
124 if (Opcodes[i] == op)
125 fprintf(stderr,"DUPLICATE OPCODES: %lx\n", op);
  /src/external/apache2/llvm/dist/llvm/lib/Object/
MachOObjectFile.cpp 3141 : E(E), O(O), Opcodes(Bytes), Ptr(Bytes.begin()),
3145 Ptr = Opcodes.begin();
3150 Ptr = Opcodes.end();
3166 if (Ptr == Opcodes.end()) {
3191 Twine::utohexstr(OpcodeStart - Opcodes.begin()));
3206 Twine::utohexstr(OpcodeStart - Opcodes.begin()));
3215 Twine::utohexstr(OpcodeStart - Opcodes.begin()));
3231 Twine::utohexstr(OpcodeStart - Opcodes.begin()));
3240 Twine::utohexstr(OpcodeStart - Opcodes.begin()));
3256 Twine::utohexstr(OpcodeStart - Opcodes.begin()))
    [all...]
  /src/external/apache2/llvm/dist/llvm/utils/vim/syntax/
machine-ir.vim 17 " Opcodes. Matching instead of listing them because individual targets can add
  /src/external/apache2/llvm/lib/libclangAST/
Makefile 111 CLANG_TABLEGEN_SRC= Opcodes.td
113 Opcodes.inc|-gen-clang-opcodes
  /src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/
llvm-exegesis.cpp 53 cl::desc("opcode to measure, by index, or -1 to measure all opcodes"),
58 cl::desc("comma-separated list of opcodes to measure, by name"),
169 "default all such opcodes are filtered out. this flag will "
170 "instead show only such unstable opcodes"),
312 const auto Opcodes = getOpcodesOrDie(State.getInstrInfo());
332 if (!Opcodes.empty()) {
333 for (const unsigned Opcode : Opcodes) {
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
LegalizerInfo.cpp 443 std::initializer_list<unsigned> Opcodes) {
444 unsigned Representative = *Opcodes.begin();
446 assert(!llvm::empty(Opcodes) && Opcodes.begin() + 1 != Opcodes.end() &&
447 "Initializer list must have at least two opcodes");
449 for (unsigned Op : llvm::drop_begin(Opcodes))
722 errs() << "The following opcodes have ill-defined legalization rules:";

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