HomeSort by: relevance | last modified time | path
    Searched refs:OrigReg (Results 1 - 10 of 10) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
TailDuplicator.h 101 void addSSAUpdateEntry(Register OrigReg, Register NewReg,
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64A57FPLoadBalancing.cpp 555 Register OrigReg = U.getReg();
556 U.setReg(Substs[OrigReg]);
560 ToErase.push_back(OrigReg);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
TailDuplicator.cpp 331 void TailDuplicator::addSSAUpdateEntry(Register OrigReg, Register NewReg,
334 SSAUpdateVals.find(OrigReg);
340 SSAUpdateVals.insert(std::make_pair(OrigReg, Vals));
341 SSAUpdateVRs.push_back(OrigReg);
InlineSpiller.cpp 1245 /// i.e., there should be a living sibling of OrigReg at the insert point.
1257 Register OrigReg = OrigLI.reg();
1258 SmallSetVector<Register, 16> &Siblings = Virt2SiblingsMap[OrigReg];
1319 // to the OrigReg. It means the def instruction should dominate all the spills
SplitKit.cpp 343 unsigned OrigReg = VRM.getOriginal(CurLI->reg());
344 const LiveInterval &Orig = LIS.getInterval(OrigReg);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
RegisterBankInfo.cpp 467 Register OrigReg = MO.getReg();
469 LLVM_DEBUG(dbgs() << " changed, replace " << printReg(OrigReg, nullptr));
475 LLT OrigTy = MRI.getType(OrigReg);
LegalizerHelper.cpp 1458 Register LegalizerHelper::widenWithUnmerge(LLT WideTy, Register OrigReg) {
1460 LLT OrigTy = MRI.getType(OrigReg);
1484 UnmergeResults[0] = OrigReg;
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
LegalizerHelper.h 160 /// Widen \p OrigReg to \p WideTy by merging to a wider type, padding with
162 Register widenWithUnmerge(LLT WideTy, Register OrigReg);
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
LoopStrengthReduce.cpp 4094 const SCEV *OrigReg;
4097 : LUIdx(LI), Imm(I), OrigReg(R) {}
4107 OS << "in formulae referencing " << *OrigReg << " in use " << LUIdx
4156 const SCEV *OrigReg = J->second;
4159 const SmallBitVector &UsedByIndices = RegUses.getUsedByIndices(OrigReg);
4161 if (!isa<SCEVConstant>(OrigReg) &&
4163 LLVM_DEBUG(dbgs() << "Skipping cross-use reuse for " << *OrigReg
4190 WorkItems.push_back(WorkItem(LUIdx, Imm, OrigReg));
4205 const SCEV *OrigReg = WI.OrigReg;
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/AsmParser/
X86AsmParser.cpp 1663 unsigned OrigReg = OrigOp.Mem.BaseReg;
1669 !X86MCRegisterClasses[RegClassID].contains(OrigReg)) {
1674 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(OrigReg))
1676 else if (X86MCRegisterClasses[X86::GR32RegClassID].contains(OrigReg))
1678 else if (X86MCRegisterClasses[X86::GR16RegClassID].contains(OrigReg))
1688 if (FinalReg != OrigReg) {

Completed in 47 milliseconds