| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCCCState.cpp | 17 const SmallVectorImpl<ISD::OutputArg> &Outs) {
18 for (const auto &I : Outs) {
|
| PPCCCState.h | 23 PreAnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs);
57 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
60 IsFixed.resize(Outs.size(), false);
61 for (unsigned ValNo = 0, E = Outs.size(); ValNo != E; ++ValNo)
62 if (Outs[ValNo].IsFixed)
65 CCState::AnalyzeCallOperands(Outs, Fn);
|
| PPCISelLowering.h | 1178 bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs,
1261 const SmallVectorImpl<ISD::OutputArg> &Outs,
1265 const SmallVectorImpl<ISD::OutputArg> &Outs,
1292 const SmallVectorImpl<ISD::OutputArg> &Outs,
1299 const SmallVectorImpl<ISD::OutputArg> &Outs,
1306 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsCCState.h | 37 void PreAnalyzeReturnForF128(const SmallVectorImpl<ISD::OutputArg> &Outs);
42 PreAnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
59 PreAnalyzeReturnForVectorFloat(const SmallVectorImpl<ISD::OutputArg> &Outs);
89 AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
93 PreAnalyzeCallOperands(Outs, FuncArgs, Func);
94 CCState::AnalyzeCallOperands(Outs, Fn);
104 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
106 void AnalyzeCallOperands(const SmallVectorImpl<MVT> &Outs,
130 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
132 PreAnalyzeReturnForF128(Outs);
[all...] |
| MipsCCState.cpp | 99 const SmallVectorImpl<ISD::OutputArg> &Outs) {
101 for (unsigned i = 0; i < Outs.size(); ++i) {
121 const SmallVectorImpl<ISD::OutputArg> &Outs) {
122 for (unsigned i = 0; i < Outs.size(); ++i) {
123 ISD::OutputArg Out = Outs[i];
132 const SmallVectorImpl<ISD::OutputArg> &Outs,
135 for (unsigned i = 0; i < Outs.size(); ++i) {
136 TargetLowering::ArgListEntry FuncArg = FuncArgs[Outs[i].OrigArgIndex];
141 CallOperandIsFixed.push_back(Outs[i].IsFixed);
|
| MipsCallLowering.cpp | 399 SmallVector<ISD::OutputArg, 8> Outs;
400 subTargetRegTypeForCallingConv(F, RetInfos, OrigArgIndices, Outs);
405 CCInfo.AnalyzeReturn(Outs, TLI.CCAssignFnForReturn());
406 setLocInfo(ArgLocs, Outs);
566 SmallVector<ISD::OutputArg, 8> Outs;
567 subTargetRegTypeForCallingConv(F, ArgInfos, OrigArgIndices, Outs);
582 CCInfo.AnalyzeCallOperands(Outs, TLI.CCAssignFnForCall(), FuncOrigArgs, Call);
583 setLocInfo(ArgLocs, Outs);
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| CallingConvLower.cpp | 104 bool CCState::CheckReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
107 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
108 MVT VT = Outs[i].VT;
109 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
118 void CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
121 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
122 MVT VT = Outs[i].VT;
123 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
131 void CCState::AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
133 unsigned NumOps = Outs.size()
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZCallingConv.h | 65 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
69 for (unsigned i = 0; i < Outs.size(); ++i)
70 ArgIsFixed.push_back(Outs[i].IsFixed);
73 for (unsigned i = 0; i < Outs.size(); ++i)
74 ArgIsShortVector.push_back(IsShortVectorType(Outs[i].ArgVT));
76 CCState::AnalyzeCallOperands(Outs, Fn);
81 void AnalyzeCallOperands(const SmallVectorImpl<MVT> &Outs,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| LanaiISelLowering.h | 116 const SmallVectorImpl<ISD::OutputArg> &Outs,
144 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| LanaiISelLowering.cpp | 413 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
428 return LowerCCCCallTo(Chain, Callee, CallConv, IsVarArg, IsTailCall, Outs,
536 const SmallVectorImpl<ISD::OutputArg> &Outs,
547 CCInfo.AnalyzeReturn(Outs, RetCC_Lanai32);
598 bool /*IsTailCall*/, const SmallVectorImpl<ISD::OutputArg> &Outs,
616 CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32_VarArg);
619 CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32_Fast);
621 CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32);
629 for (unsigned I = 0, E = Outs.size(); I != E; ++I)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 144 const SmallVectorImpl<ISD::OutputArg> &Outs,
174 const SmallVectorImpl<ISD::OutputArg> &Outs,
178 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| MSP430ISelLowering.cpp | 441 const SmallVectorImpl<ISD::OutputArg> &Outs) {
442 State.AnalyzeCallOperands(Outs, CC_MSP430_AssignStack);
555 const SmallVectorImpl<ISD::OutputArg> &Outs) {
556 State.AnalyzeReturn(Outs, RetCC_MSP430);
589 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
608 Outs, OutVals, Ins, dl, DAG, InVals);
726 const SmallVectorImpl<ISD::OutputArg> &Outs,
730 return CCInfo.CheckReturn(Outs, RetCC_MSP430);
736 const SmallVectorImpl<ISD::OutputArg> &Outs,
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| SparcISelLowering.h | 144 const SmallVectorImpl<ISD::OutputArg> &Outs,
149 const SmallVectorImpl<ISD::OutputArg> &Outs,
154 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| CallingConvLower.h | 294 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
300 bool CheckReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
305 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
315 void AnalyzeArguments(const SmallVectorImpl<ISD::OutputArg> &Outs,
317 AnalyzeCallOperands(Outs, Fn);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUCallLowering.h | 34 SmallVectorImpl<BaseArgInfo> &Outs,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
| ARCISelLowering.h | 105 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| ARCISelLowering.cpp | 226 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
241 CCInfo.AnalyzeCallOperands(Outs, CC_ARC);
595 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
598 if (!CCInfo.CheckReturn(Outs, RetCC_ARC))
608 const SmallVectorImpl<ISD::OutputArg> &Outs,
626 CCInfo.AnalyzeReturn(Outs, RetCC_ARC);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| AVRISelLowering.h | 165 const SmallVectorImpl<ISD::OutputArg> &Outs,
169 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| M68kISelLowering.h | 241 const SmallVectorImpl<ISD::OutputArg> &Outs,
268 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| M68kISelLowering.cpp | 181 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
182 if (Outs.empty())
185 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
471 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
481 StructReturnType SR = callIsStructReturn(Outs);
505 MF.getFunction().hasStructRetAttr(), CLI.RetTy, Outs, OutVals, Ins,
526 CCInfo.AnalyzeCallOperands(Outs, CC_M68k);
558 if (!Outs.empty() && Outs.back().Flags.isInAlloca())
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelLowering.h | 84 const SmallVectorImpl<ISD::OutputArg> &Outs,
87 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
| XCoreISelLowering.h | 154 const SmallVectorImpl<ISD::OutputArg> &Outs,
221 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 371 auto &Outs = CLI.Outs;
396 CCInfo.AnalyzeCallOperands(Outs, getHasAlu32() ? CC_BPF32 : CC_BPF64);
400 if (Outs.size() > MaxArgs)
403 for (auto &Arg : Outs) {
502 const SmallVectorImpl<ISD::OutputArg> &Outs,
520 CCInfo.AnalyzeReturn(Outs, getHasAlu32() ? RetCC_BPF32 : RetCC_BPF64);
|
| BPFISelLowering.h | 101 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| CallLowering.h | 458 /// \return True if the return type described by \p Outs can be returned
460 bool checkReturn(CCState &CCInfo, SmallVectorImpl<BaseArgInfo> &Outs,
466 SmallVectorImpl<BaseArgInfo> &Outs,
475 /// described by \p Outs can fit into the return registers. If false
478 SmallVectorImpl<BaseArgInfo> &Outs,
|
