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  /src/external/gpl3/gdb/dist/sim/bfin/
linux-fixed-code.s 28 P0 = 173;
34 R0 = [P0];
35 [P0] = R1;
40 R0 = [P0];
43 [P0] = R2;
49 R1 = [P0];
51 [P0] = R0;
56 R1 = [P0];
58 [P0] = R0;
63 R1 = [P0];
    [all...]
  /src/external/gpl3/gdb.old/dist/sim/bfin/
linux-fixed-code.s 28 P0 = 173;
34 R0 = [P0];
35 [P0] = R1;
40 R0 = [P0];
43 [P0] = R2;
49 R1 = [P0];
51 [P0] = R0;
56 R1 = [P0];
58 [P0] = R0;
63 R1 = [P0];
    [all...]
  /src/external/gpl3/gdb/dist/sim/testsuite/bfin/
testset2.s 13 loadsym P0, datalabel;
17 R0 = B [ P0 ] (Z);
19 TESTSET ( P0 );
22 R0 = B [ P0 ] (Z);
27 TESTSET ( P0 );
30 R0 = B [ P0 ] (Z);
a1.s 11 P0 = 63;
12 R0 = P0; DBGA ( R0.L , 63 );
13 P0 = -64;
14 R0 = P0; DBGA ( R0.L , 0xffc0 );
23 P0.L = 0x2222;
24 R0 = P0; DBGA ( R0.L , 0x2222 );
26 P0.H = 0x2222;
27 R0 = P0; DBGA ( R0.H , 0x2222 );
mem3.s 9 loadsym P0, data0;
11 [ P0 ] = R0;
12 P1 = [ P0 ];
14 R1 = [ P0 ];
19 W [ P0 ] = R0;
20 R1 = W [ P0 ] (Z);
28 B [ P0 ] = R0;
29 R1 = B [ P0 ] (Z);
s0.s 7 P0 = R0;
8 LSETUP ( ls0 , ls0 ) LC0 = P0;
lp0.s 8 P0 = 3;
10 LSETUP ( out0 , out1 ) LC0 = P0;
12 LSETUP ( out1 , out1 ) LC1 = P0;
c_progctrl_csync_mmr.S 54 LD32(p0, EVT); // Setup Event Vectors and Handlers
56 [ P0 ++ ] = R0;
59 [ P0 ++ ] = R0;
62 [ P0 ++ ] = R0;
65 [ P0 ++ ] = R0;
67 [ P0 ++ ] = R0; // IVT4 not used
70 [ P0 ++ ] = R0;
73 [ P0 ++ ] = R0;
76 [ P0 ++ ] = R0;
79 [ P0 ++ ] = R0
    [all...]
c_mmr_timer.S 48 LD32(p0, EVT0); // Setup Event Vectors and Handlers
50 [ P0 ++ ] = R0;
53 [ P0 ++ ] = R0;
56 [ P0 ++ ] = R0;
59 [ P0 ++ ] = R0;
61 [ P0 ++ ] = R0; // EVT4 not used global Interr Enable (INT4)
64 [ P0 ++ ] = R0;
67 [ P0 ++ ] = R0;
69 [ P0 ++ ] = R0;
72 [ P0 ++ ] = R0
    [all...]
l0.s 7 loadsym P0, tab;
8 R0 = [ P0 ++ ];
9 R1 = [ P0 ++ ];
10 R2 = [ P0 ++ ];
11 R3 = [ P0 ++ ];
12 R4 = [ P0 ++ ];
13 R5 = [ P0 ++ ];
14 R6 = [ P0 ++ ];
15 R7 = [ P0 ++ ];
26 loadsym P0, tab2
    [all...]
issue129.s 10 P0.L = 0x0000;
11 P0.H = 0x8000;
16 P4 += P0 (BREV);
24 P0.L = 0x0000;
25 P0.H = 0xE000;
30 P4 += P0 (BREV);
stk.s 22 loadsym P0, a;
23 _DBG P0;
24 SP = P0;
25 FP = P0;
26 P1 = [ P0 ++ ];
27 P2 = [ P0 ++ ];
28 P0 += 4;
29 P4 = [ P0 ++ ];
30 P5 = [ P0 ++ ];
c_interr_timer_tcount.S 63 LD32(p0, EVT); // Setup Event Vectors and Handlers
66 [ P0 ++ ] = R0;
69 [ P0 ++ ] = R0;
72 [ P0 ++ ] = R0;
75 [ P0 ++ ] = R0;
77 [ P0 ++ ] = R0; // IVT4 not used
80 [ P0 ++ ] = R0;
83 [ P0 ++ ] = R0;
86 [ P0 ++ ] = R0;
89 [ P0 ++ ] = R0
    [all...]
issue126.s 12 P1 = ( P1 + P0 ) << 2;
13 P2 = ( P2 + P0 ) << 1;
  /src/external/gpl3/gdb.old/dist/sim/testsuite/bfin/
testset2.s 13 loadsym P0, datalabel;
17 R0 = B [ P0 ] (Z);
19 TESTSET ( P0 );
22 R0 = B [ P0 ] (Z);
27 TESTSET ( P0 );
30 R0 = B [ P0 ] (Z);
a1.s 11 P0 = 63;
12 R0 = P0; DBGA ( R0.L , 63 );
13 P0 = -64;
14 R0 = P0; DBGA ( R0.L , 0xffc0 );
23 P0.L = 0x2222;
24 R0 = P0; DBGA ( R0.L , 0x2222 );
26 P0.H = 0x2222;
27 R0 = P0; DBGA ( R0.H , 0x2222 );
mem3.s 9 loadsym P0, data0;
11 [ P0 ] = R0;
12 P1 = [ P0 ];
14 R1 = [ P0 ];
19 W [ P0 ] = R0;
20 R1 = W [ P0 ] (Z);
28 B [ P0 ] = R0;
29 R1 = B [ P0 ] (Z);
s0.s 7 P0 = R0;
8 LSETUP ( ls0 , ls0 ) LC0 = P0;
lp0.s 8 P0 = 3;
10 LSETUP ( out0 , out1 ) LC0 = P0;
12 LSETUP ( out1 , out1 ) LC1 = P0;
c_progctrl_csync_mmr.S 54 LD32(p0, EVT); // Setup Event Vectors and Handlers
56 [ P0 ++ ] = R0;
59 [ P0 ++ ] = R0;
62 [ P0 ++ ] = R0;
65 [ P0 ++ ] = R0;
67 [ P0 ++ ] = R0; // IVT4 not used
70 [ P0 ++ ] = R0;
73 [ P0 ++ ] = R0;
76 [ P0 ++ ] = R0;
79 [ P0 ++ ] = R0
    [all...]
c_mmr_timer.S 48 LD32(p0, EVT0); // Setup Event Vectors and Handlers
50 [ P0 ++ ] = R0;
53 [ P0 ++ ] = R0;
56 [ P0 ++ ] = R0;
59 [ P0 ++ ] = R0;
61 [ P0 ++ ] = R0; // EVT4 not used global Interr Enable (INT4)
64 [ P0 ++ ] = R0;
67 [ P0 ++ ] = R0;
69 [ P0 ++ ] = R0;
72 [ P0 ++ ] = R0
    [all...]
l0.s 7 loadsym P0, tab;
8 R0 = [ P0 ++ ];
9 R1 = [ P0 ++ ];
10 R2 = [ P0 ++ ];
11 R3 = [ P0 ++ ];
12 R4 = [ P0 ++ ];
13 R5 = [ P0 ++ ];
14 R6 = [ P0 ++ ];
15 R7 = [ P0 ++ ];
26 loadsym P0, tab2
    [all...]
issue129.s 10 P0.L = 0x0000;
11 P0.H = 0x8000;
16 P4 += P0 (BREV);
24 P0.L = 0x0000;
25 P0.H = 0xE000;
30 P4 += P0 (BREV);
stk.s 22 loadsym P0, a;
23 _DBG P0;
24 SP = P0;
25 FP = P0;
26 P1 = [ P0 ++ ];
27 P2 = [ P0 ++ ];
28 P0 += 4;
29 P4 = [ P0 ++ ];
30 P5 = [ P0 ++ ];
c_interr_timer_tcount.S 63 LD32(p0, EVT); // Setup Event Vectors and Handlers
66 [ P0 ++ ] = R0;
69 [ P0 ++ ] = R0;
72 [ P0 ++ ] = R0;
75 [ P0 ++ ] = R0;
77 [ P0 ++ ] = R0; // IVT4 not used
80 [ P0 ++ ] = R0;
83 [ P0 ++ ] = R0;
86 [ P0 ++ ] = R0;
89 [ P0 ++ ] = R0
    [all...]

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1 2 3 4 5 6 7 8 91011>>