| /src/external/gpl3/gdb/dist/sim/testsuite/bfin/ |
| issue129.s | 13 P4.L = 0x0000;
14 P4.H = 0x8000;
16 P4 += P0 (BREV);
18 R0 = P4;
27 P4.L = 0x1f09;
28 P4.H = 0x9008;
30 P4 += P0 (BREV);
32 R0 = P4;
|
| s2.s | 7 P4 = 0;
11 P2 = P1 + ( P4 << 1 );
14 R2 = P4;
35 P4 += 1;
36 CC = P4 < 4 (IU);
|
| c_br_preg_killed_ac.s | 19 P4 = 4;
30 JUMP ( PC + P4 ); //brf LABEL2; // (bp);
33 JUMP ( PC + P4 ); //brf LABEL3; // (bp);
36 JUMP ( PC + P4 ); //brf LABEL4;
39 JUMP ( PC + P4 ); //brf LABEL5;
42 JUMP ( PC + P4 ); //brf LABEL6;
45 JUMP ( PC + P4 ); //brf LABEL7; // (bp);
48 JUMP ( PC + P4 ); //brf LABEL8;
51 JUMP ( PC + P4 ); //brf LABEL9;
54 JUMP ( PC + P4 ); //brf LABELCHK1
[all...] |
| c_pushpopmultiple_preg.s | 16 P4 = 0xa4 (X);
22 P4 = 0;
28 CHECKREG p4, 0x000000a4;
33 P4 = 0xb4 (X);
38 P4 = 0;
44 CHECKREG p4, 0x000000b4;
48 P4 = 0xc4 (X);
52 P4 = 0;
58 CHECKREG p4, 0x000000c4;
61 P4 = 0xd4 (X)
[all...] |
| testset.s | 11 [P4] = R0;
12 FLUSHINV[P4];
19 TESTSET (P4);
35 R2 = [P4];
36 FLUSHINV[P4];
50 loadsym P4, _data
|
| c_regmv_pr_pr.s | 11 imm32 p4, 0x20081009;
17 imm32 p4, 0x20081009;
22 P4 = P1;
27 CHECKREG p4, 0x20021003;
33 imm32 p4, 0x20081009;
38 P4 = P2;
43 CHECKREG p4, 0x20041005;
49 imm32 p4, 0x20081009;
52 P1 = P4;
53 P2 = P4;
[all...] |
| c_comp3op_pr_plus_pr_sh1.s | 11 imm32 p4, 0x23451899;
18 P4 = P1 + ( P4 << 1 );
25 CHECKREG p4, 0xE38B8AFF;
33 imm32 p4, 0x23456829;
40 P4 = P2 + ( P4 << 1 );
47 CHECKREG p4, 0x49F49ED6;
55 imm32 p4, 0x23456893;
62 P4 = P3 + ( P4 << 1 )
[all...] |
| c_comp3op_pr_plus_pr_sh2.s | 11 imm32 p4, 0x23451899;
18 P4 = P1 + ( P4 << 2 );
25 CHECKREG p4, 0x3D6BF80F;
33 imm32 p4, 0x23456829;
40 P4 = P2 + ( P4 << 2 );
47 CHECKREG p4, 0x3D70A380;
55 imm32 p4, 0x23456893;
62 P4 = P3 + ( P4 << 2 )
[all...] |
| c_ptr2op_pr_shadd_1_2.s | 16 imm32 p4, 0xa00a1089;
23 P4 = ( P4 + P1 ) << 1;
30 CHECKREG p4, 0x49354142;
38 imm32 p4, 0x20081009;
45 P4 = ( P4 + P2 ) << 2;
52 CHECKREG p4, 0x40A240C4;
60 imm32 p4, 0x2d081089;
67 P4 = ( P4 + P3 ) << 2
[all...] |
| c_compi2opp_pr_eq_i7_n.s | 12 P4 = -4;
20 CHECKREG p4, -4;
29 P4 = -12;
37 CHECKREG p4, -12;
46 P4 = -20;
54 CHECKREG p4, -20;
63 P4 = -28;
71 CHECKREG p4, -28;
80 P4 = -36;
88 CHECKREG p4, -36
[all...] |
| c_compi2opp_pr_eq_i7_p.s | 12 P4 = 4;
19 CHECKREG p4, 4;
27 P4 = 12;
34 CHECKREG p4, 12;
42 P4 = 20;
49 CHECKREG p4, 20;
57 P4 = 28;
64 CHECKREG p4, 28;
73 P4 = 36;
81 CHECKREG p4, 36
[all...] |
| c_compi2opp_pr_add_i7_p.s | 15 P4 += 4;
21 CHECKREG p4, 0x00000004;
28 P4 += 12;
34 CHECKREG p4, 0x00000010;
41 P4 += 20;
47 CHECKREG p4, 0x00000024;
54 P4 += 28;
60 CHECKREG p4, 0x00000040;
67 P4 += 36;
73 CHECKREG p4, 0x00000064
[all...] |
| c_ptr2op_pr_neg_pr.s | 12 imm32 p4, 0x200a1009;
19 P4 -= P1;
26 CHECKREG p4, 0x200A1009;
34 imm32 p4, 0x20081009;
41 P4 -= P2;
48 CHECKREG p4, 0x20081009;
56 imm32 p4, 0x20081009;
63 P4 -= P3;
70 CHECKREG p4, 0x20081009;
78 imm32 p4, 0x200d1009
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/testsuite/bfin/ |
| issue129.s | 13 P4.L = 0x0000;
14 P4.H = 0x8000;
16 P4 += P0 (BREV);
18 R0 = P4;
27 P4.L = 0x1f09;
28 P4.H = 0x9008;
30 P4 += P0 (BREV);
32 R0 = P4;
|
| s2.s | 7 P4 = 0;
11 P2 = P1 + ( P4 << 1 );
14 R2 = P4;
35 P4 += 1;
36 CC = P4 < 4 (IU);
|
| c_br_preg_killed_ac.s | 19 P4 = 4;
30 JUMP ( PC + P4 ); //brf LABEL2; // (bp);
33 JUMP ( PC + P4 ); //brf LABEL3; // (bp);
36 JUMP ( PC + P4 ); //brf LABEL4;
39 JUMP ( PC + P4 ); //brf LABEL5;
42 JUMP ( PC + P4 ); //brf LABEL6;
45 JUMP ( PC + P4 ); //brf LABEL7; // (bp);
48 JUMP ( PC + P4 ); //brf LABEL8;
51 JUMP ( PC + P4 ); //brf LABEL9;
54 JUMP ( PC + P4 ); //brf LABELCHK1
[all...] |
| c_pushpopmultiple_preg.s | 16 P4 = 0xa4 (X);
22 P4 = 0;
28 CHECKREG p4, 0x000000a4;
33 P4 = 0xb4 (X);
38 P4 = 0;
44 CHECKREG p4, 0x000000b4;
48 P4 = 0xc4 (X);
52 P4 = 0;
58 CHECKREG p4, 0x000000c4;
61 P4 = 0xd4 (X)
[all...] |
| testset.s | 11 [P4] = R0;
12 FLUSHINV[P4];
19 TESTSET (P4);
35 R2 = [P4];
36 FLUSHINV[P4];
50 loadsym P4, _data
|
| c_regmv_pr_pr.s | 11 imm32 p4, 0x20081009;
17 imm32 p4, 0x20081009;
22 P4 = P1;
27 CHECKREG p4, 0x20021003;
33 imm32 p4, 0x20081009;
38 P4 = P2;
43 CHECKREG p4, 0x20041005;
49 imm32 p4, 0x20081009;
52 P1 = P4;
53 P2 = P4;
[all...] |
| c_comp3op_pr_plus_pr_sh1.s | 11 imm32 p4, 0x23451899;
18 P4 = P1 + ( P4 << 1 );
25 CHECKREG p4, 0xE38B8AFF;
33 imm32 p4, 0x23456829;
40 P4 = P2 + ( P4 << 1 );
47 CHECKREG p4, 0x49F49ED6;
55 imm32 p4, 0x23456893;
62 P4 = P3 + ( P4 << 1 )
[all...] |
| c_comp3op_pr_plus_pr_sh2.s | 11 imm32 p4, 0x23451899;
18 P4 = P1 + ( P4 << 2 );
25 CHECKREG p4, 0x3D6BF80F;
33 imm32 p4, 0x23456829;
40 P4 = P2 + ( P4 << 2 );
47 CHECKREG p4, 0x3D70A380;
55 imm32 p4, 0x23456893;
62 P4 = P3 + ( P4 << 2 )
[all...] |
| c_ptr2op_pr_shadd_1_2.s | 16 imm32 p4, 0xa00a1089;
23 P4 = ( P4 + P1 ) << 1;
30 CHECKREG p4, 0x49354142;
38 imm32 p4, 0x20081009;
45 P4 = ( P4 + P2 ) << 2;
52 CHECKREG p4, 0x40A240C4;
60 imm32 p4, 0x2d081089;
67 P4 = ( P4 + P3 ) << 2
[all...] |
| c_compi2opp_pr_eq_i7_n.s | 12 P4 = -4;
20 CHECKREG p4, -4;
29 P4 = -12;
37 CHECKREG p4, -12;
46 P4 = -20;
54 CHECKREG p4, -20;
63 P4 = -28;
71 CHECKREG p4, -28;
80 P4 = -36;
88 CHECKREG p4, -36
[all...] |
| c_compi2opp_pr_eq_i7_p.s | 12 P4 = 4;
19 CHECKREG p4, 4;
27 P4 = 12;
34 CHECKREG p4, 12;
42 P4 = 20;
49 CHECKREG p4, 20;
57 P4 = 28;
64 CHECKREG p4, 28;
73 P4 = 36;
81 CHECKREG p4, 36
[all...] |
| c_compi2opp_pr_add_i7_p.s | 15 P4 += 4;
21 CHECKREG p4, 0x00000004;
28 P4 += 12;
34 CHECKREG p4, 0x00000010;
41 P4 += 20;
47 CHECKREG p4, 0x00000024;
54 P4 += 28;
60 CHECKREG p4, 0x00000040;
67 P4 += 36;
73 CHECKREG p4, 0x00000064
[all...] |
