| /src/external/gpl3/gcc/dist/libgcc/config/bfin/ |
| crti.S | 39 [--SP] = P5;
45 P5 = [P5 + _current_shared_library_p5_offset_]
52 [--SP] = P5;
58 P5 = [P5 + _current_shared_library_p5_offset_]
|
| crtn.S | 37 P5 = [SP++];
46 P5 = [SP++];
|
| /src/external/gpl3/gcc.old/dist/libgcc/config/bfin/ |
| crti.S | 39 [--SP] = P5;
45 P5 = [P5 + _current_shared_library_p5_offset_]
52 [--SP] = P5;
58 P5 = [P5 + _current_shared_library_p5_offset_]
|
| crtn.S | 37 P5 = [SP++];
46 P5 = [SP++];
|
| /src/external/gpl3/gdb/dist/sim/testsuite/bfin/ |
| c_pushpopmultiple_preg.s | 17 P5 = 0xa5 (X);
18 [ -- SP ] = ( P5:1 );
23 P5 = 0;
24 ( P5:1 ) = [ SP ++ ];
29 CHECKREG p5, 0x000000a5;
34 P5 = 0xb5 (X);
35 [ -- SP ] = ( P5:2 );
39 P5 = 0;
40 ( P5:2 ) = [ SP ++ ];
45 CHECKREG p5, 0x000000b5
[all...] |
| 10272_small.s | 6 loadsym P5, tmp0;
9 W[p5+0x6] = r6;
14 R1 = W[P5 + 0x6 ] (X);
16 W[P5+0x6] = R0;
18 R5=W[P5+0x6] (X);
25 loadsym P5, tmp0;
28 W[p5+0x6] = r6;
29 R1 = W[P5 + 0x6 ] (X);
31 W[P5+0x6] = R0;
33 R5=W[P5+0x6] (X)
[all...] |
| stk5.s | 15 [ -- SP ] = ( R7:7, P5:4 );
20 ( R7:7, P5:4 ) = [ SP ++ ];
31 P5 = 8;
32 SP = SP + P5;
|
| c_regmv_pr_pr.s | 12 imm32 p5, 0x200a100b;
18 imm32 p5, 0x200a100b;
23 P5 = P1;
28 CHECKREG p5, 0x20021003;
34 imm32 p5, 0x200a100b;
39 P5 = P2;
44 CHECKREG p5, 0x20041005;
50 imm32 p5, 0x200a100b;
55 P5 = P4;
60 CHECKREG p5, 0x20081009
[all...] |
| c_comp3op_pr_plus_pr_sh1.s | 12 imm32 p5, 0x78911345;
19 P5 = P1 + ( P5 << 1 );
26 CHECKREG p5, 0x8E238057;
34 imm32 p5, 0x78912325;
41 P5 = P2 + ( P5 << 1 );
48 CHECKREG p5, 0xF48C14CE;
56 imm32 p5, 0x78912343;
63 P5 = P3 + ( P5 << 1 )
[all...] |
| c_comp3op_pr_plus_pr_sh2.s | 12 imm32 p5, 0x78911345;
19 P5 = P1 + ( P5 << 2 );
26 CHECKREG p5, 0x929BE2BF;
34 imm32 p5, 0x78912325;
41 P5 = P2 + ( P5 << 2 );
48 CHECKREG p5, 0x929F8F70;
56 imm32 p5, 0x78912343;
63 P5 = P3 + ( P5 << 2 )
[all...] |
| c_ptr2op_pr_shadd_1_2.s | 17 imm32 p5, 0x400a300b;
24 P5 = ( P5 + P1 ) << 2;
31 CHECKREG p5, 0x126B008C;
39 imm32 p5, 0xf00a900b;
46 P5 = ( P5 + P2 ) << 2;
53 CHECKREG p5, 0x80AC40CC;
61 imm32 p5, 0xf00ab07b;
68 P5 = ( P5 + P3 ) << 2
[all...] |
| c_compi2opp_pr_eq_i7_n.s | 13 P5 = -5;
21 CHECKREG p5, -5;
30 P5 = -13;
38 CHECKREG p5, -13;
47 P5 = -21;
55 CHECKREG p5, -21;
64 P5 = -29;
72 CHECKREG p5, -29;
81 P5 = -37;
89 CHECKREG p5, -37
[all...] |
| stk6.s | 12 P5.L = 0xdead;
21 ( R7:0, P5:0 ) = [ SP ++ ];
36 R0 = P5; DBGA ( R0.L , 14 );
39 [ -- SP ] = ( R7:0, P5:0 );
40 ( R7:0, P5:0 ) = [ SP ++ ];
55 R0 = P5; DBGA ( R0.L , 14 );
|
| c_compi2opp_pr_eq_i7_p.s | 13 P5 = 5;
20 CHECKREG p5, 5;
28 P5 = 13;
35 CHECKREG p5, 13;
43 P5 = 21;
50 CHECKREG p5, 21;
58 P5 = 29;
65 CHECKREG p5, 29;
74 P5 = 37;
82 CHECKREG p5, 37
[all...] |
| cec-system-call.S | 9 # This test keeps P5 as the base of the EVT table
13 [P5 + 4 * \lvl\()] = R1;
19 imm32 P5, EVT0;
20 P1 = P5;
|
| /src/external/gpl3/gdb.old/dist/sim/testsuite/bfin/ |
| c_pushpopmultiple_preg.s | 17 P5 = 0xa5 (X);
18 [ -- SP ] = ( P5:1 );
23 P5 = 0;
24 ( P5:1 ) = [ SP ++ ];
29 CHECKREG p5, 0x000000a5;
34 P5 = 0xb5 (X);
35 [ -- SP ] = ( P5:2 );
39 P5 = 0;
40 ( P5:2 ) = [ SP ++ ];
45 CHECKREG p5, 0x000000b5
[all...] |
| 10272_small.s | 6 loadsym P5, tmp0;
9 W[p5+0x6] = r6;
14 R1 = W[P5 + 0x6 ] (X);
16 W[P5+0x6] = R0;
18 R5=W[P5+0x6] (X);
25 loadsym P5, tmp0;
28 W[p5+0x6] = r6;
29 R1 = W[P5 + 0x6 ] (X);
31 W[P5+0x6] = R0;
33 R5=W[P5+0x6] (X)
[all...] |
| stk5.s | 15 [ -- SP ] = ( R7:7, P5:4 );
20 ( R7:7, P5:4 ) = [ SP ++ ];
31 P5 = 8;
32 SP = SP + P5;
|
| c_regmv_pr_pr.s | 12 imm32 p5, 0x200a100b;
18 imm32 p5, 0x200a100b;
23 P5 = P1;
28 CHECKREG p5, 0x20021003;
34 imm32 p5, 0x200a100b;
39 P5 = P2;
44 CHECKREG p5, 0x20041005;
50 imm32 p5, 0x200a100b;
55 P5 = P4;
60 CHECKREG p5, 0x20081009
[all...] |
| c_comp3op_pr_plus_pr_sh1.s | 12 imm32 p5, 0x78911345;
19 P5 = P1 + ( P5 << 1 );
26 CHECKREG p5, 0x8E238057;
34 imm32 p5, 0x78912325;
41 P5 = P2 + ( P5 << 1 );
48 CHECKREG p5, 0xF48C14CE;
56 imm32 p5, 0x78912343;
63 P5 = P3 + ( P5 << 1 )
[all...] |
| c_comp3op_pr_plus_pr_sh2.s | 12 imm32 p5, 0x78911345;
19 P5 = P1 + ( P5 << 2 );
26 CHECKREG p5, 0x929BE2BF;
34 imm32 p5, 0x78912325;
41 P5 = P2 + ( P5 << 2 );
48 CHECKREG p5, 0x929F8F70;
56 imm32 p5, 0x78912343;
63 P5 = P3 + ( P5 << 2 )
[all...] |
| c_ptr2op_pr_shadd_1_2.s | 17 imm32 p5, 0x400a300b;
24 P5 = ( P5 + P1 ) << 2;
31 CHECKREG p5, 0x126B008C;
39 imm32 p5, 0xf00a900b;
46 P5 = ( P5 + P2 ) << 2;
53 CHECKREG p5, 0x80AC40CC;
61 imm32 p5, 0xf00ab07b;
68 P5 = ( P5 + P3 ) << 2
[all...] |
| c_compi2opp_pr_eq_i7_n.s | 13 P5 = -5;
21 CHECKREG p5, -5;
30 P5 = -13;
38 CHECKREG p5, -13;
47 P5 = -21;
55 CHECKREG p5, -21;
64 P5 = -29;
72 CHECKREG p5, -29;
81 P5 = -37;
89 CHECKREG p5, -37
[all...] |
| stk6.s | 12 P5.L = 0xdead;
21 ( R7:0, P5:0 ) = [ SP ++ ];
36 R0 = P5; DBGA ( R0.L , 14 );
39 [ -- SP ] = ( R7:0, P5:0 );
40 ( R7:0, P5:0 ) = [ SP ++ ];
55 R0 = P5; DBGA ( R0.L , 14 );
|
| c_compi2opp_pr_eq_i7_p.s | 13 P5 = 5;
20 CHECKREG p5, 5;
28 P5 = 13;
35 CHECKREG p5, 13;
43 P5 = 21;
50 CHECKREG p5, 21;
58 P5 = 29;
65 CHECKREG p5, 29;
74 P5 = 37;
82 CHECKREG p5, 37
[all...] |
