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    Searched refs:PB0_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN__SHIFT (Results 1 - 3 of 3) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/bif/
bif_3_0_sh_mask.h 639 #define PB0_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN__SHIFT 0x00000000
bif_4_1_sh_mask.h 3722 #define PB0_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN__SHIFT 0x0
bif_5_0_sh_mask.h 4172 #define PB0_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN__SHIFT 0x0

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