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Searched refs:PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5_MASK (Results 1 - 3 of 3) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/bif/
bif_3_0_sh_mask.h	`704 #define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5_MASK 0x00c00000L`
bif_4_1_sh_mask.h	`3647 #define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5_MASK 0xc00000`
bif_5_0_sh_mask.h	`4097 #define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5_MASK 0xc00000`

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