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    Searched refs:PCI_BAR0 (Results 1 - 25 of 27) sorted by relevancy

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  /src/sys/dev/pci/
pucdata.c 60 { PUC_PORT_TYPE_COM, PCI_BAR0, 0x00, COM_FREQ * 8 },
70 { PUC_PORT_TYPE_COM, PCI_BAR0, 0x00, COM_FREQ * 8 },
71 { PUC_PORT_TYPE_COM, PCI_BAR0, 0x08, COM_FREQ * 8 },
72 { PUC_PORT_TYPE_COM, PCI_BAR0, 0x10, COM_FREQ * 8 },
73 { PUC_PORT_TYPE_COM, PCI_BAR0, 0x18, COM_FREQ * 8 },
82 { PUC_PORT_TYPE_COM, PCI_BAR0, 0x00, COM_FREQ * 8 },
83 { PUC_PORT_TYPE_COM, PCI_BAR0, 0x08, COM_FREQ * 8 },
84 { PUC_PORT_TYPE_COM, PCI_BAR0, 0x10, COM_FREQ * 8 },
85 { PUC_PORT_TYPE_COM, PCI_BAR0, 0x18, COM_FREQ * 8 },
95 { PUC_PORT_TYPE_COM, PCI_BAR0, 0x00, COM_FREQ * 8 }
    [all...]
if_eqos_pci.c 120 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, PCI_BAR0);
121 if (pci_mapreg_map(pa, PCI_BAR0, memtype, 0, &memt, &memh, NULL,
chipsfb.c 112 sc->sc_fb = (pci_conf_read(scp->sc_pc, scp->sc_pcitag, PCI_BAR0) &
if_ex_pci.c 342 base0 = pci_conf_read(pc, tag, PCI_BAR0);
349 pci_conf_write(pc, tag, PCI_BAR0, base0);
pci_map.c 307 if (reg >= PCI_BAR0 && reg <= PCI_BAR5)
308 wanted_bei = PCI_EA_BEI_BAR0 + ((reg - PCI_BAR0) / 4);
hdaudio_pci.c 148 reg = PCI_BAR0;
igma.c 348 if (pci_mapreg_map(pa, PCI_BAR0, PCI_MAPREG_TYPE_MEM,
ismt.c 679 if (pci_mapreg_map(pa, PCI_BAR0, PCI_MAPREG_TYPE_MEM, 0,
  /src/sys/dev/cardbus/
cardbusreg.h 49 # define CARDBUS_CIS_ASI_BAR(x) (((CARDBUS_CIS_ASIMASK & (x))-1)*4+PCI_BAR0)
if_malo_cardbus.c 113 error = Cardbus_mapreg_map(ct, PCI_BAR0,
127 Cardbus_mapreg_unmap(ct, PCI_BAR0, sc->sc_mem1_bt,
164 Cardbus_mapreg_unmap(ct, PCI_BAR0, sc->sc_mem1_bt,
181 Cardbus_conf_write(ct, csc->sc_tag, PCI_BAR0, csc->sc_bar1_val);
com_cardbus.c 91 PCI_BAR0, PCI_MAPREG_TYPE_IO },
93 PCI_BAR0, PCI_MAPREG_TYPE_IO },
95 PCI_BAR0, PCI_MAPREG_TYPE_IO },
97 PCI_BAR0, PCI_MAPREG_TYPE_IO },
99 PCI_BAR0, PCI_MAPREG_TYPE_IO },
if_fxp_cardbus.c 138 } else if (Cardbus_mapreg_map(csc->ct, PCI_BAR0,
189 PCI_BAR0, csc->base0_reg);
258 reg = PCI_BAR0;
if_ral_cardbus.c 154 error = Cardbus_mapreg_map(ct, PCI_BAR0,
191 Cardbus_mapreg_unmap(ct, PCI_BAR0, sc->sc_st, sc->sc_sh,
243 Cardbus_conf_write(ct, csc->sc_tag, PCI_BAR0, csc->sc_bar_val);
if_ex_cardbus.c 239 if (Cardbus_mapreg_map(ct, PCI_BAR0, PCI_MAPREG_TYPE_IO, 0,
241 csc->sc_bar_reg = PCI_BAR0;
327 Cardbus_mapreg_unmap(ct, PCI_BAR0, sc->sc_iot,
njata_cardbus.c 50 #define NJATA32_CARDBUS_BASEADDR_IO PCI_BAR0
njs_cardbus.c 53 #define NJSC32_CARDBUS_BASEADDR_IO PCI_BAR0
adv_cardbus.c 63 #define ADV_CARDBUS_IOBA PCI_BAR0
cardbus.c 532 cardbus_conf_write(cc, cf, tag, PCI_BAR0, 0);
  /src/sys/arch/x86/pci/
dwiic_pci.c 236 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, PCI_BAR0);
237 if (pci_mapreg_map(pa, PCI_BAR0, memtype, 0, &sc->sc_dwiic.sc_iot,
270 pci_conf_read(sc->sc_pc, sc->sc_ptag, PCI_BAR0));
272 pci_conf_read(sc->sc_pc, sc->sc_ptag, PCI_BAR0 + 0x4));
msipic.c 712 bar = PCI_BAR0;
  /src/sys/arch/arm/nvidia/
tegra_xusb.c 661 DPRINTF(sc->sc_dev, "%s fpci PCI_BAR0 = 0x%x\n", __func__,
662 bus_space_read_4(bst, fpcih, PCI_BAR0));
664 bus_space_write_4(bst, fpcih, PCI_BAR0, 0x10000000);
665 DPRINTF(sc->sc_dev, "%s fpci PCI_BAR0 = 0x%x\n", __func__,
666 bus_space_read_4(bst, fpcih, PCI_BAR0));
  /src/sys/arch/arm/cortex/
gic_v2m.c 295 bar = PCI_BAR0 + (4 * (tbl & PCI_MSIX_TBLBIR_MASK));
gicv3_its.c 655 bar = PCI_BAR0 + (4 * (tbl & PCI_MSIX_TBLBIR_MASK));
  /src/sys/arch/arm/apple/
apple_pcie.c 645 bar = PCI_BAR0 + (4 * (tbl & PCI_MSIX_TBLBIR_MASK));
  /src/sys/arch/arm/nxp/
imxpcie.c 566 PCIE_WRITE(sc, PCI_BAR0, 0x00000004);

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