| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/amlogic/ |
| meson-gxl-s905d-p230.dts | 63 /* P230 has exclusive choice between internal or external PHY */
68 /* Select external PHY by default */
69 phy-handle = <&external_phy>;
73 /* External PHY is in RGMII */
74 phy-mode = "rgmii";
78 external_phy: ethernet-phy@0 {
83 /* External PHY reset is shared with internal PHY Led signal */
|
| meson-gxm-q200.dts | 45 /* Q200 has exclusive choice between internal or external PHY */
50 /* Select external PHY by default */
51 phy-handle = <&external_phy>;
55 /* External PHY is in RGMII */
56 phy-mode = "rgmii";
60 external_phy: ethernet-phy@0 {
65 /* External PHY reset is shared with internal PHY Led signal */
|
| meson-gxm-vega-s96.dts | 23 /* Select external PHY by default */
24 phy-handle = <&external_phy>;
28 /* External PHY is in RGMII */
29 phy-mode = "rgmii";
33 external_phy: ethernet-phy@0 {
|
| meson-gxl-s905d-p231.dts | 17 /* P231 has only internal PHY port */
19 phy-mode = "rmii";
20 phy-handle = <&internal_phy>;
|
| meson-gxm-q201.dts | 17 /* Q201 has only internal PHY port */
19 phy-mode = "rmii";
20 phy-handle = <&internal_phy>;
|
| /src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/starfive/ |
| jh7100-starfive-visionfive-v1.dts | 22 phy-handle = <&phy>;
26 * The board uses a Motorcomm YT8521 PHY supporting RGMII-ID, but requires
32 * which uses a Microchip PHY. Hence, most likely the Motorcomm PHY is the one
36 phy: ethernet-phy@0 { label
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/marvell/ |
| armada-8040-mcbin.dts | 20 phy0: ethernet-phy@0 {
21 compatible = "ethernet-phy-ieee802.3-c45";
26 phy8: ethernet-phy@8 {
27 compatible = "ethernet-phy-ieee802.3-c45";
35 /* Network PHY */
36 phy = <&phy0>;
37 phy-mode = "10gbase-r";
42 /* Network PHY */
43 phy = <&phy8>;
44 phy-mode = "10gbase-r"
[all...] |
| cn9132-db.dtsi | 106 phy-mode = "10gbase-r";
107 /* Generic PHY, providing serdes lanes */
157 /* Generic PHY, providing serdes lanes */
167 /* Generic PHY, providing serdes lanes */
176 /* Generic PHY, providing serdes lanes */
213 usb-phy = <&cp2_usb3_0_phy0>;
215 phy-names = "usb";
222 usb-phy = <&cp2_usb3_0_phy1>;
223 /* Generic PHY, providing serdes lanes */
225 phy-names = "usb", "utmi"
[all...] |
| cn9131-db.dtsi | 88 phy-mode = "10gbase-r";
89 /* Generic PHY, providing serdes lanes */
118 /* Generic PHY, providing serdes lanes */
128 /* Generic PHY, providing serdes lanes */
201 usb-phy = <&cp1_usb3_0_phy0>;
202 /* Generic PHY, providing serdes lanes */
204 phy-names = "usb", "utmi";
|
| armada-7040-db.dts | 118 phy-names = "cp0-pcie2-x1-phy";
217 phy-names = "cp0-sata0-1-phy";
228 phy-supply = <&cp0_reg_usb3_0_vbus>;
234 phy-names = "cp0-usb3h0-comphy", "utmi";
242 phy-supply = <&cp0_reg_usb3_1_vbus>;
248 phy-names = "cp0-usb3h1-comphy", "utmi";
270 phy0: ethernet-phy@0 {
273 phy1: ethernet-phy@1
[all...] |
| armada-8040-mcbin.dtsi | 113 * Not stable in HS modes - phy needs "more calibration", so add
116 marvell,xenon-phy-slow-mode;
174 ge_phy: ethernet-phy@0 {
188 phy-names = "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy",
189 "cp0-pcie0-x4-lane2-phy", "cp0-pcie0-x4-lane3-phy";
238 /* Generic PHY, providing serdes lanes */
248 phy-names = "cp0-sata0-1-phy"
[all...] |
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/allwinner/ |
| sun50i-a64-pine64-plus.dts | 16 phy-mode = "rgmii-txid";
17 phy-handle = <&ext_rgmii_phy>;
22 ext_rgmii_phy: ethernet-phy@1 {
23 compatible = "ethernet-phy-ieee802.3-c22";
30 * Ethernet PHY needs 30ms to properly power up and some more
|
| sun50i-h5-libretech-all-h5-cc.dts | 33 /* This board has external PHY */
37 phy-supply = <®_gmac_3v3>;
38 phy-handle = <&ext_rgmii_phy>;
39 phy-mode = "rgmii-id";
45 ext_rgmii_phy: ethernet-phy@1 {
46 compatible = "ethernet-phy-ieee802.3-c22";
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/freescale/ |
| fsl-ls1028a-kontron-sl28-var2.dts | 21 phy0: ethernet-phy@5 {
27 phy1: ethernet-phy@4 {
37 * In the base device tree the PHY was registered in the mdio
38 * subnode as it is PHY for this port. On this module this PHY
40 * Therefore, delete the mdio subnode as well as the phy-handle
43 /delete-property/ phy-handle;
58 phy-handle = <&phy0>;
59 phy-mode = "sgmii";
66 phy-handle = <&phy1>
[all...] |
| fsl-lx2160a-rdb.dts | 41 phy-handle = <&aquantia_phy1>;
42 phy-connection-type = "usxgmii";
47 phy-handle = <&aquantia_phy2>;
48 phy-connection-type = "usxgmii";
53 phy-handle = <&rgmii_phy1>;
54 phy-connection-type = "rgmii-id";
58 phy-handle = <&rgmii_phy2>;
59 phy-connection-type = "rgmii-id";
65 rgmii_phy1: ethernet-phy@1 {
66 /* AR8035 PHY */
[all...] |
| fsl-ls1028a-kontron-kbox-a-230-ls.dts | 5 * This consists of a Kontron SMARC-sAL28 (Dual PHY) and a special
40 /* BCM54140 QSGMII quad PHY */
41 qsgmii_phy0: ethernet-phy@7 {
45 qsgmii_phy1: ethernet-phy@8 {
49 qsgmii_phy2: ethernet-phy@9 {
53 qsgmii_phy3: ethernet-phy@10 {
77 phy-handle = <&qsgmii_phy0>;
78 phy-mode = "qsgmii";
85 phy-handle = <&qsgmii_phy1>;
86 phy-mode = "qsgmii"
[all...] |
| fsl-ls1028a-kontron-sl28-var4.dts | 17 model = "Kontron SMARC-sAL28 (Dual PHY)";
22 phy-handle = <&phy1>;
23 phy-connection-type = "rgmii-id";
30 phy1: ethernet-phy@4 {
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| imx28-eukrea-mbmx287lc.dts | 8 * Module contains : i.MX287 + 128MB DDR2 + NAND + 2 x Ethernet PHY + RTC
24 phy-mode = "rmii";
27 phy-reset-gpios = <&gpio3 27 GPIO_ACTIVE_LOW>;
|
| imx28-eukrea-mbmx283lc.dts | 8 * Module contains : i.MX282 + 64MB DDR2 + NAND + Ethernet PHY + RTC
43 phy-mode = "rmii";
46 phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>;
|
| imx28-duckbill-2.dts | 58 mac0_phy_reset_pin: mac0-phy-reset@0 {
61 MX28_PAD_GPMI_ALE__GPIO_0_26 /* PHY Reset */
68 mac0_phy_int_pin: mac0-phy-int@0 {
71 MX28_PAD_GPMI_D07__GPIO_0_7 /* PHY Interrupt */
127 phy-mode = "rmii";
130 phy-supply = <®_3p3v>;
131 phy-reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
132 phy-reset-duration = <25>;
133 phy-handle = <ðphy>;
140 ethphy: ethernet-phy@0
[all...] |
| imx7d-flex-concentrator.dts | 145 phy-mode = "rmii";
146 phy-handle = <ðphy>;
150 * MDIO bus reset is used to generate PHY device reset before
151 * Ethernet PHY type ID auto-detection. Otherwise this communication
164 ethphy: ethernet-phy@1 {
165 compatible = "ethernet-phy-ieee802.3-c22";
234 /* PHY reset: SRE_FAST, DSE_X1 */
236 /* Clock from PHY to MAC: 100kPU */
238 /* PHY interrupt: 100kPU, HYS */
|
| imx6ul-prti6g.dts | 92 phy-mode = "rmii";
93 phy-handle = <&rmii_phy>;
106 /* Microchip KSZ8081RNA PHY */
107 rmii_phy: ethernet-phy@0 {
267 /* PHY ENET1_RST */
269 /* PHY ENET1_IRQ */
|
| am3874-iceboard.dts | 44 * provided no -id/-txid/-rxid suffix is provided to "phy-mode".
46 * The receive path is delayed at the PHY. The recommended register settings
48 * conversion code in the kernel lies: the PHY's registers are 120 ps per tap,
54 phy-handle = <ðphy0>;
55 phy-mode = "rgmii";
59 phy-handle = <ðphy1>;
60 phy-mode = "rgmii";
65 ethphy0: ethernet-phy@0 {
76 phy-reset-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
79 ethphy1: ethernet-phy@1
[all...] |
| imx28-duckbill-2-485.dts | 58 mac0_phy_reset_pin: mac0-phy-reset@0 {
61 MX28_PAD_GPMI_ALE__GPIO_0_26 /* PHY Reset */
68 mac0_phy_int_pin: mac0-phy-int@0 {
71 MX28_PAD_GPMI_D07__GPIO_0_7 /* PHY Interrupt */
123 phy-mode = "rmii";
126 phy-supply = <®_3p3v>;
127 phy-reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
128 phy-reset-duration = <25>;
129 phy-handle = <ðphy>;
136 ethphy: ethernet-phy@0
[all...] |
| /src/sys/rump/dev/lib/libmiiphy/ |
| Makefile | 9 COMMENT=MII and PHY drivers (for networking)
|
