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    Searched refs:PHYCLKPerState (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/
display_mode_vba.h 405 double PHYCLKPerState[DC__VOLTAGE_STATES + 1];
amdgpu_display_mode_vba.c 265 mode_lib->vba.PHYCLKPerState[i] = soc->clock_limits[i].phyclk_mhz;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn20/
amdgpu_display_mode_vba_20.c 4064 dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24,
4077 if (mode_lib->vba.PHYCLKPerState[i] >= 270.0) {
4106 if (mode_lib->vba.Outbpp == BPP_INVALID && mode_lib->vba.PHYCLKPerState[i] >= 540.0) {
4136 && mode_lib->vba.PHYCLKPerState[i]
amdgpu_display_mode_vba_20v2.c 4108 dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24,
4121 if (mode_lib->vba.PHYCLKPerState[i] >= 270.0) {
4150 if (mode_lib->vba.Outbpp == BPP_INVALID && mode_lib->vba.PHYCLKPerState[i] >= 540.0) {
4180 && mode_lib->vba.PHYCLKPerState[i]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn21/
amdgpu_display_mode_vba_21.c 4144 dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24,
4158 if (mode_lib->vba.PHYCLKPerState[i] >= 270.0) {
4189 if (mode_lib->vba.Outbpp == BPP_INVALID && mode_lib->vba.PHYCLKPerState[i] >= 540.0) {
4221 && mode_lib->vba.PHYCLKPerState[i]

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