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    Searched refs:PIPE0_LATENCY_CONTROL (Results 1 - 2 of 2) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/radeon/
evergreend.h	1214 #define PIPE0_LATENCY_CONTROL 0x0bf4
radeon_evergreen.c	2294 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset, 2302 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,

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