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    Searched refs:PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT (Results 1 - 6 of 6) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_6_0_sh_mask.h 8170 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x0000001c
dce_8_0_sh_mask.h 38 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
dce_10_0_sh_mask.h 38 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
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dce_11_0_sh_mask.h 38 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
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dce_11_2_sh_mask.h 38 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
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dce_12_0_sh_mask.h 3303 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
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