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Searched refs:PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE_MASK (Results 1 - 5 of 5) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_6_0_sh_mask.h	`8269 #define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE_MASK 0x10000000L`
dce_8_0_sh_mask.h	`107 #define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE_MASK 0x10000000`
dce_10_0_sh_mask.h	`107 #define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE_MASK 0x10000000 [all...]`
dce_11_2_sh_mask.h	`107 #define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE_MASK 0x10000000 [all...]`
dce_12_0_sh_mask.h	`3360 #define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE_MASK 0x10000000L [all...]`

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