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    Searched refs:PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE_MASK (Results 1 - 4 of 4) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_6_0_sh_mask.h 8275 #define PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE_MASK 0x20000000L
dce_8_0_sh_mask.h 109 #define PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE_MASK 0x20000000
dce_10_0_sh_mask.h 109 #define PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE_MASK 0x20000000
    [all...]
dce_11_2_sh_mask.h 109 #define PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE_MASK 0x20000000
    [all...]

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