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    Searched refs:PIPESTAT (Results 1 - 6 of 6) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_fifo_underrun.c 51 * is no interrupt (despite that the signalling bit is in the PIPESTAT pipe
98 i915_reg_t reg = PIPESTAT(crtc->pipe);
119 i915_reg_t reg = PIPESTAT(pipe);
intel_display.c 18695 error->pipe[i].stat = I915_READ(PIPESTAT(i));
  /src/sys/external/bsd/drm2/dist/drm/i915/
i915_irq.c 462 i915_reg_t reg = PIPESTAT(pipe);
485 i915_reg_t reg = PIPESTAT(pipe);
514 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
1292 I915_WRITE(PIPESTAT(pipe),
1317 * PIPESTAT bits get signalled even when the interrupt is
1345 reg = PIPESTAT(pipe);
1586 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1669 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
i915_debugfs.c 480 I915_READ(PIPESTAT(pipe)));
569 I915_READ(PIPESTAT(pipe)));
609 I915_READ(PIPESTAT(pipe)));
i915_reg.h 5875 #define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT)
  /src/sys/external/bsd/drm2/dist/drm/i915/gvt/
handlers.c 1992 MMIO_D(PIPESTAT(PIPE_A), D_ALL);
1993 MMIO_D(PIPESTAT(PIPE_B), D_ALL);
1994 MMIO_D(PIPESTAT(PIPE_C), D_ALL);
1995 MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);

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