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    Searched refs:PIPE_CONTROL_L3_RO_CACHE_INVALIDATE (Results 1 - 2 of 2) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/i915/gt/
intel_gpu_commands.h	240 #define PIPE_CONTROL_L3_RO_CACHE_INVALIDATE REG_BIT(10) /* gen12 */
intel_lrc.c	4053 flags |= PIPE_CONTROL_L3_RO_CACHE_INVALIDATE;

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