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    Searched refs:PIXEL_RATE_CNTL (Results 1 - 4 of 4) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_clock_source.h 74 SRII(PIXEL_RATE_CNTL, OTG, 0),\
75 SRII(PIXEL_RATE_CNTL, OTG, 1),\
76 SRII(PIXEL_RATE_CNTL, OTG, 2),\
77 SRII(PIXEL_RATE_CNTL, OTG, 3),\
78 SRII(PIXEL_RATE_CNTL, OTG, 4),\
79 SRII(PIXEL_RATE_CNTL, OTG, 5)
91 SRII(PIXEL_RATE_CNTL, OTG, 0),\
92 SRII(PIXEL_RATE_CNTL, OTG, 1),\
93 SRII(PIXEL_RATE_CNTL, OTG, 2),\
94 SRII(PIXEL_RATE_CNTL, OTG, 3
    [all...]
amdgpu_dce_hwseq.c 176 REG_UPDATE(PIXEL_RATE_CNTL[tg_inst],
186 REG_UPDATE(PIXEL_RATE_CNTL[tg_inst],
192 REG_UPDATE_2(PIXEL_RATE_CNTL[tg_inst],
dce_hwseq.h 68 SRII(PIXEL_RATE_CNTL, blk, inst), \
72 SRII(PIXEL_RATE_CNTL, blk, 0), \
73 SRII(PIXEL_RATE_CNTL, blk, 1), \
74 SRII(PIXEL_RATE_CNTL, blk, 2), \
75 SRII(PIXEL_RATE_CNTL, blk, 3), \
76 SRII(PIXEL_RATE_CNTL, blk, 4), \
77 SRII(PIXEL_RATE_CNTL, blk, 5)
345 uint32_t PIXEL_RATE_CNTL[6];
463 HWS_SF1(blk, PIXEL_RATE_CNTL, PIXEL_RATE_SOURCE, mask_sh),\
464 HWS_SF(blk, PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh
    [all...]
amdgpu_dce_clock_source.c 924 REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);

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