Searched refs:PLL4 (Results 1 - 11 of 11) sorted by relevance

/src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
H A Dqcom,lcc-ipq806x.h11 #define PLL4 0 macro
H A Dqcom,lcc-msm8960.h11 #define PLL4 0 macro
H A Dstm32mp13-clks.h24 #define PLL4 9 macro
H A Dstm32mp1-clks.h188 #define PLL4 179 macro
/src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/st/
H A Dstm32mp157c-odyssey.dts41 assigned-clock-rates = <125000000>; /* Clock PLL4 to 750Mhz in ATF/U-Boot */
H A Dstm32mp15xc-lxa-tac.dtsi230 assigned-clock-rates = <125000000>; /* Clock PLL4 to 750Mhz in ATF */
/src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/qcom/
H A Dqcom-mdm9615.dtsi108 <&lcc PLL4>;
H A Dqcom-msm8960.dtsi136 <&lcc PLL4>;
H A Dqcom-apq8064.dtsi721 <&lcc PLL4>;
H A Dqcom-ipq8064.dtsi501 clocks = <&pxo_board>, <&cxo_board>, <&lcc PLL4>;
/src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/ti/
H A Dk3-am65-main.dtsi1019 * Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via

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