HomeSort by: relevance | last modified time | path
    Searched refs:PLL4 (Results 1 - 6 of 6) sorted by relevancy

  /src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
qcom,lcc-ipq806x.h 11 #define PLL4 0
qcom,lcc-mdm9615.h 13 #define PLL4 0
qcom,lcc-msm8960.h 11 #define PLL4 0
stm32mp1-clks.h 188 #define PLL4 179
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
stm32mp157c-odyssey.dts 35 assigned-clock-rates = <125000000>; /* Clock PLL4 to 750Mhz in ATF/U-Boot */
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/ti/
k3-am65-main.dtsi 849 * Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via

Completed in 15 milliseconds