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    Searched refs:PLL_CNTL__PLL_RESET_MASK (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_ci_baco.c 96 { CMD_READMODIFYWRITE, mmPLL_CNTL, PLL_CNTL__PLL_RESET_MASK, PLL_CNTL__PLL_RESET__SHIFT, 0, 0x1 },
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_6_0_sh_mask.h 8327 #define PLL_CNTL__PLL_RESET_MASK 0x00000001L
dce_8_0_sh_mask.h 2089 #define PLL_CNTL__PLL_RESET_MASK 0x1
dce_10_0_sh_mask.h 11643 #define PLL_CNTL__PLL_RESET_MASK 0x1
    [all...]
dce_11_0_sh_mask.h 11455 #define PLL_CNTL__PLL_RESET_MASK 0x1
    [all...]

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