Searched refs:PLL_VPLL (Results 1 - 25 of 37) sorted by relevance
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| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/rockchip/ |
| H A D | rk3566-powkiddy-rgb10max3.dts | 21 <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
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| H A D | rk3566-powkiddy-rgb30.dts | 17 <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
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| H A D | rk3566-powkiddy-rk2023.dts | 17 <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
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| H A D | rk3568-wolfvision-pf5-display.dtsi | 42 assigned-clocks = <&cru PLL_VPLL>;
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| H A D | rk3566-anbernic-rg353x.dtsi | 82 <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
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| H A D | rk3566-anbernic-rg-arc.dtsi | 80 <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
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| H A D | rk3566-anbernic-rg503.dts | 171 <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
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| H A D | rk3566-radxa-cm3-io.dts | 268 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
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| H A D | rk3566-powkiddy-x55.dts | 352 <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
907 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
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| H A D | rk3566-radxa-zero-3.dtsi | 517 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
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| H A D | rk3568-fastrhino-r66s.dtsi | 454 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
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| H A D | rk3566-pinetab2.dtsi | 265 <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
923 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
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| H A D | rk3566-box-demo.dts | 469 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
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| H A D | rk3566-lubancat-1.dts | 576 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
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| H A D | rk3566-odroid-m1s.dts | 650 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
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| H A D | rk3566-orangepi-3b.dtsi | 665 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
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| H A D | rk3568-roc-pc.dts | 634 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
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| H A D | rk3568-wolfvision-pf5.dts | 515 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
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| H A D | rk3568-evb1-v10.dts | 676 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
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| H A D | rk3568-nanopi-r5s.dtsi | 577 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
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| H A D | rk3566-anbernic-rgxx3.dtsi | 706 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
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| H A D | rk3566-lckfb-tspi.dts | 712 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
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| /src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/ |
| H A D | rockchip,rk3576-cru.h | 20 #define PLL_VPLL 2 macro
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| H A D | rk3568-cru.h | 76 #define PLL_VPLL 5 macro
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| H A D | rk3399-cru.h | 19 #define PLL_VPLL 7 macro
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