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    Searched refs:PORT_CLK_SEL (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/i915/gvt/
display.c 232 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &=
234 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |=
252 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &=
254 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |=
272 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &=
274 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |=
handlers.c 2429 MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
2430 MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
2431 MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
2432 MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
2433 MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_ddi.c 1150 I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
3148 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
3171 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
3894 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
intel_display.c 10669 u32 ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
  /src/sys/external/bsd/drm2/dist/drm/i915/
i915_reg.h 9869 #define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B)
9880 /* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */
9881 #define DDI_CLK_SEL(port) PORT_CLK_SEL(port)

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