| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCPredicates.cpp | 1 //===-- PPCPredicates.cpp - PPC Branch Predicate Information --------------===//
18 PPC::Predicate PPC::InvertPredicate(PPC::Predicate Opcode) {
20 case PPC::PRED_EQ: return PPC::PRED_NE;
21 case PPC::PRED_NE: return PPC::PRED_EQ;
22 case PPC::PRED_LT: return PPC::PRED_GE
[all...] |
| PPCMCTargetDesc.h | 16 // GCC #defines PPC on Linux but we use it as our namespace name
17 #undef PPC
44 /// Construct an PPC ELF object writer.
47 /// Construct a PPC Mach-O object writer.
51 /// Construct a PPC XCOFF object writer.
108 // Generated files will use "namespace PPC". To avoid symbol clash,
109 // undefine PPC here. PPC may be predefined on some hosts.
110 #undef PPC
161 static const MCPhysReg RRegs[32] = PPC_REGS0_31(PPC::R);
[all...] |
| PPCFixupKinds.h | 1 //===-- PPCFixupKinds.h - PPC Specific Fixup Entries ------------*- C++ -*-===//
14 #undef PPC
17 namespace PPC {
|
| PPCInstPrinter.cpp | 1 //===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===//
9 // This class prints an PPC MCInst to a .s file.
33 FullRegNames("ppc-asm-full-reg-names", cl::Hidden, cl::init(false),
38 ShowVSRNumsAsVR("ppc-vsr-nums-as-vr", cl::Hidden, cl::init(false),
43 FullRegNamesWithPercent("ppc-reg-with-percent-prefix", cl::Hidden,
63 (MI->getOpcode() == PPC::ADDIS8 || MI->getOpcode() == PPC::ADDIS) &&
96 if (MI->getOpcode() == PPC::PLDpc) {
114 if (MI->getOpcode() == PPC::RLWINM) {
137 if (MI->getOpcode() == PPC::RLDICR |
[all...] |
| PPCAsmBackend.cpp | 1 //===-- PPCAsmBackend.cpp - PPC Assembler Backend -------------------------===//
35 case PPC::fixup_ppc_nofixup:
37 case PPC::fixup_ppc_brcond14:
38 case PPC::fixup_ppc_brcond14abs:
40 case PPC::fixup_ppc_br24:
41 case PPC::fixup_ppc_br24abs:
42 case PPC::fixup_ppc_br24_notoc:
44 case PPC::fixup_ppc_half16:
46 case PPC::fixup_ppc_half16ds:
48 case PPC::fixup_ppc_pcrel34
[all...] |
| PPCPredicates.h | 1 //===-- PPCPredicates.h - PPC Branch Predicate Information ------*- C++ -*-===//
16 // GCC #defines PPC on Linux but we use it as our namespace name
17 #undef PPC
19 // Generated files will use "namespace PPC". To avoid symbol clash,
20 // undefine PPC here. PPC may be predefined on some hosts.
21 #undef PPC
24 namespace PPC {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCCallingConv.cpp | 20 // gracefully fallback to PPC C calling convention on Release builds.
37 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
38 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
62 PPC::R3, PPC::R4, PPC::R5, PPC::R6
[all...] |
| PPCInstrInfo.cpp | 15 #include "PPC.h"
46 #define DEBUG_TYPE "ppc-instr-info"
65 opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
68 static cl::opt<bool> DisableCmpOpt("disable-ppc-cmp-opt",
71 static cl::opt<bool> VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy",
76 UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden,
80 FMARPFactor("ppc-fma-rp-factor", cl::Hidden, cl::init(1.5),
84 "ppc-fma-rp-reduction", cl::Hidden, cl::init(true),
91 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP
[all...] |
| PPCRegisterInfo.cpp | 55 EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true),
59 AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false),
63 EnableGPRToVecSpills("ppc-enable-gpr-to-vsr-spills", cl::Hidden, cl::init(false),
67 StackPtrConst("ppc-stack-ptr-caller-preserved",
73 MaxCRBitSpillDist("ppc-max-crbit-spill-dist",
75 "spill on ppc"),
87 ReportAccMoves("ppc-report-acc-moves",
96 : PPCGenRegisterInfo(TM.isPPC64() ? PPC::LR8 : PPC::LR,
100 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX
[all...] |
| PPCRegisterInfo.h | 28 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
29 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
30 Reg = PPC::CR0;
31 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
32 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
33 Reg = PPC::CR1
[all...] |
| PPCInstrInfo.h | 26 /// PPC.td and PPCInstrFormats.td.
134 #define NoInstr PPC::INSTRUCTION_LIST_END
137 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
138 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX,
[all...] |
| PPCTLSDynamicCall.cpp | 23 #include "PPC.h"
36 #define DEBUG_TYPE "ppc-tls-dynamic-call"
61 if (MI.getOpcode() != PPC::ADDItlsgdLADDR &&
62 MI.getOpcode() != PPC::ADDItlsldLADDR &&
63 MI.getOpcode() != PPC::ADDItlsgdLADDR32 &&
64 MI.getOpcode() != PPC::ADDItlsldLADDR32 &&
65 MI.getOpcode() != PPC::TLSGDAIX &&
66 MI.getOpcode() != PPC::TLSGDAIX8 && !IsPCREL) {
71 if (MI.getOpcode() == PPC::ADJCALLSTACKDOWN)
73 else if (MI.getOpcode() == PPC::ADJCALLSTACKUP
[all...] |
| PPCFastISel.cpp | 16 #include "PPC.h"
145 return RC->getID() == PPC::VSFRCRegClassID;
148 return RC->getID() == PPC::VSSRCRegClassID;
160 const PPC::Predicate Pred);
163 unsigned FP64LoadOpc = PPC::LFD);
201 static Optional<PPC::Predicate> getComparePred(CmpInst::Predicate Pred) {
229 return Optional<PPC::Predicate>();
233 return PPC::PRED_EQ;
238 return PPC::PRED_GT;
243 return PPC::PRED_GE
[all...] |
| PPCPreEmitPeephole.cpp | 14 #include "PPC.h"
30 #define DEBUG_TYPE "ppc-pre-emit-peephole"
42 EnablePCRelLinkerOpt("ppc-pcrel-linker-opt", cl::Hidden, cl::init(true),
46 RunPreEmitPeephole("ppc-late-peephole", cl::Hidden, cl::init(true),
55 case PPC::LBZ:
56 case PPC::LBZ8:
57 case PPC::LHA:
58 case PPC::LHA8:
59 case PPC::LHZ:
60 case PPC::LHZ8
[all...] |
| PPCMIPeephole.cpp | 23 #include "PPC.h"
40 #define DEBUG_TYPE "ppc-mi-peepholes"
52 "Number of functions entered in PPC MI Peepholes");
64 FixedPointRegToImm("ppc-reg-to-imm-fixed-point", cl::Hidden, cl::init(true),
69 ConvertRegReg("ppc-convert-rr-to-ri", cl::Hidden, cl::init(true),
73 EnableSExtElimination("ppc-eliminate-signext",
78 EnableZExtElimination("ppc-eliminate-zeroext",
132 assert((MF.getRegInfo().use_empty(PPC::X2) ||
172 if (Opcode == PPC::RLDICL || Opcode == PPC::RLDICL_rec |
[all...] |
| PPCVSXSwapRemoval.cpp | 44 #include "PPC.h"
60 #define DEBUG_TYPE "ppc-vsx-swaps"
168 return (isRegInClass(Reg, &PPC::VSRCRegClass) ||
169 isRegInClass(Reg, &PPC::VRRCRegClass));
174 return (isRegInClass(Reg, &PPC::VSFRCRegClass) ||
175 isRegInClass(Reg, &PPC::VSSRCRegClass));
288 case PPC::XXPERMDI: {
337 case PPC::LVX:
344 case PPC::LXVD2X:
345 case PPC::LXVW4X
[all...] |
| PPCHazardRecognizers.cpp | 66 if (!PredMCID || PredMCID->getSchedClass() != PPC::Sched::IIC_SprMTSPR)
81 namespace llvm { namespace PPC { extern int getNonRecordFormOpcode(uint16_t); } }
95 case PPC::Sched::IIC_IntDivW:
96 case PPC::Sched::IIC_IntDivD:
97 case PPC::Sched::IIC_LdStLoadUpd:
98 case PPC::Sched::IIC_LdStLDU:
99 case PPC::Sched::IIC_LdStLFDU:
100 case PPC::Sched::IIC_LdStLFDUX:
101 case PPC::Sched::IIC_LdStLHA:
102 case PPC::Sched::IIC_LdStLHAU
[all...] |
| PPCFrameLowering.cpp | 1 //===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===//
9 // This file contains the PPC implementation of TargetFrameLowering class.
38 EnablePEVectorSpills("ppc-enable-pe-vector-spills",
97 {PPC::F31, -8}, \
98 {PPC::F30, -16}, \
99 {PPC::F29, -24}, \
100 {PPC::F28, -32}, \
101 {PPC::F27, -40}, \
102 {PPC::F26, -48}, \
103 {PPC::F25, -56},
[all...] |
| PPCTOCRegDeps.cpp | 64 #include "PPC.h"
83 #define DEBUG_TYPE "ppc-toc-reg-deps"
97 if (MI.getOpcode() == PPC::LDtocL ||
98 MI.getOpcode() == PPC::ADDItocL ||
99 MI.getOpcode() == PPC::LWZtocL)
115 const unsigned TOCReg = isPPC64 ? PPC::X2 : PPC::R2;
|
| PPCBranchSelector.cpp | 18 #include "PPC.h"
31 #define DEBUG_TYPE "ppc-branch-select"
73 INITIALIZE_PASS(PPCBSel, "ppc-branch-select", "PowerPC Branch Selector",
112 !Fn.getRegInfo().use_empty(PPC::X2))
335 if (I->getOpcode() == PPC::BCC && !I->getOperand(2).isImm())
337 else if ((I->getOpcode() == PPC::BC || I->getOpcode() == PPC::BCn) &&
340 else if ((I->getOpcode() == PPC::BDNZ8 || I->getOpcode() == PPC::BDNZ ||
341 I->getOpcode() == PPC::BDZ8 || I->getOpcode() == PPC::BDZ) &
[all...] |
| PPCAsmPrinter.cpp | 22 #include "PPC.h"
173 return "Linux PPC Assembly Printer";
212 "cannot create AIX PPC Assembly Printer for a little-endian target");
215 StringRef getPassName() const override { return "AIX PPC Assembly Printer"; }
326 Reg = PPC::VSX32 + (Reg - PPC::V0);
328 Reg = PPC::VSX32 + (Reg - PPC::VF0);
414 MII->getOpcode() == PPC::DBG_VALUE ||
424 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::NOP))
[all...] |
| PPCISelDAGToDAG.cpp | 1 //===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//
10 // converting from a legalized dag to a PPC dag.
16 #include "PPC.h"
70 #define DEBUG_TYPE "ppc-codegen"
88 cl::opt<bool> ANDIGlueBug("expose-ppc-andi-glue-bug",
89 cl::desc("expose the ANDI glue bug on PPC"), cl::Hidden);
92 UseBitPermRewriter("ppc-use-bit-perm-rewriter", cl::init(true),
93 cl::desc("use aggressive ppc isel for bit permutations"),
96 "ppc-bit-perm-rewriter-stress-rotates",
97 cl::desc("stress rotate selection in aggressive ppc isel for
[all...] |
| PPCCTRLoops.cpp | 22 #include "PPC.h"
47 #define DEBUG_TYPE "ppc-ctrloops-verify"
73 INITIALIZE_PASS_BEGIN(PPCCTRLoopsVerify, "ppc-ctr-loops-verify",
76 INITIALIZE_PASS_END(PPCCTRLoopsVerify, "ppc-ctr-loops-verify",
87 if (MO.isDef() && (MO.getReg() == PPC::CTR || MO.getReg() == PPC::CTR8))
90 if (MO.clobbersPhysReg(PPC::CTR) || MO.clobbersPhysReg(PPC::CTR8))
119 if (Opc == PPC::MTCTRloop || Opc == PPC::MTCTR8loop)
[all...] |
| PPCEarlyReturn.cpp | 15 #include "PPC.h"
35 #define DEBUG_TYPE "ppc-early-ret"
60 (I->getOpcode() != PPC::BLR && I->getOpcode() != PPC::BLR8) ||
76 if (J->getOpcode() == PPC::B) {
89 } else if (J->getOpcode() == PPC::BCC) {
94 MI->setDesc(TII->get(PPC::BCCLR));
106 } else if (J->getOpcode() == PPC::BC || J->getOpcode() == PPC::BCn) {
112 TII->get(J->getOpcode() == PPC::BC ? PPC::BCLR : PPC::BCLRn))
[all...] |
| /src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/PowerPC/ |
| Target.cpp | 10 #include "PPC.h"
46 return PPC::LI;
48 return PPC::LI8;
70 return TT.isArch64Bit() ? PPC::X13 : PPC::R13;
85 setMemOp(IT, DispOpIdx, MCOperand::createReg(PPC::X1));
96 unsigned ScratchImmReg = PPC::X11;
98 if (PPC::GPRCRegClass.contains(Reg))
100 if (PPC::G8RCRegClass.contains(Reg))
102 if (PPC::F4RCRegClass.contains(Reg)
[all...] |
