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    Searched refs:PP_CONTROL (Results 1 - 6 of 6) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_lvds.c 164 pps->powerdown_on_reset = I915_READ(PP_CONTROL(0)) & PANEL_POWER_RESET;
211 val = I915_READ(PP_CONTROL(0));
215 I915_WRITE(PP_CONTROL(0), val);
323 I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON);
339 I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) & ~PANEL_POWER_ON);
intel_dp.c 949 return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
1074 regs->pp_ctrl = PP_CONTROL(pps_idx);
1079 /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
1125 pp_ctrl_reg = PP_CONTROL(pipe);
2679 /* Read the current pp_control value, unlocking the register if it
2741 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2808 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
intel_display.c 1222 pp_reg = PP_CONTROL(0);
1244 pp_reg = PP_CONTROL(pipe);
1249 pp_reg = PP_CONTROL(0);
16628 u32 val = I915_READ(PP_CONTROL(pps_idx));
16631 I915_WRITE(PP_CONTROL(pps_idx), val);
  /src/sys/external/bsd/drm/dist/shared-core/
i915_suspend.c 315 dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);
486 I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
i915_reg.h 729 #define PP_CONTROL 0x61204
  /src/sys/external/bsd/drm2/dist/drm/i915/
i915_reg.h 4895 #define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL)

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